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26.5
Interrupt Sources............................................................................................................. 1434
26.5.1
Interrupt and DMA Transfer Request Signals ................................................ 1434
26.5.2
Timing of Status Registers Updates................................................................ 1436
26.6
Usage Notes .................................................................................................................... 1436
26.6.1
Stopping and Resuming Buffering Alone during Decoding ........................... 1436
26.6.2
When CROMST0 Status Register Bits are Set ............................................... 1436
26.6.3
Link Blocks..................................................................................................... 1437
26.6.4
Stopping and Resuming CD-DSP Operation .................................................. 1437
26.6.5
Note on Clearing the IREADY Flag ............................................................... 1437
26.6.6
Note on Stream Data Transfer (1)................................................................... 1438
26.6.7
Note on Stream Data Transfer (2)................................................................... 1438
Section 27 A/D Converter ............................................................................... 1439
27.1
Features........................................................................................................................... 1439
27.2
Input/Output Pins............................................................................................................ 1441
27.3
Register Descriptions...................................................................................................... 1442
27.3.1
A/D Data Registers A to H (ADDRA to ADDRH) ........................................ 1443
27.3.2
A/D Control/Status Register (ADCSR) .......................................................... 1444
27.4
Operation ........................................................................................................................ 1448
27.4.1
Single Mode.................................................................................................... 1448
27.4.2
Multi Mode ..................................................................................................... 1451
27.4.3
Scan Mode ...................................................................................................... 1453
27.4.4
A/D Converter Activation by External Trigger or
Multi-Function Timer Pulse Unit 2................................................................ 1456
27.4.5
Input Sampling and A/D Conversion Time .................................................... 1456
27.4.6
External Trigger Input Timing........................................................................ 1459
27.5
Interrupt Sources and DMA Transfer Request ............................................................... 1460
27.6
Definitions of A/D Conversion Accuracy....................................................................... 1461
27.7
Usage Notes .................................................................................................................... 1462
27.7.1
Module Standby Mode Setting ....................................................................... 1462
27.7.2
Setting Analog Input Voltage ......................................................................... 1462
27.7.3
Notes on Board Design ................................................................................... 1462
27.7.4
Processing of Analog Input Pins..................................................................... 1463
27.7.5
Permissible Signal Source Impedance ............................................................ 1464
27.7.6
Influences on Absolute Precision.................................................................... 1465
27.7.7
A/D Conversion in Deep Standby Mode ........................................................ 1465
27.7.8
Note on Usage in Scan Mode and Multi Mode............................................... 1465
Section 28 NAND Flash Memory Controller.................................................. 1467
28.1
Features........................................................................................................................... 1467