參數(shù)資料
型號(hào)： R1Q2A3609BBG-50RB
元件分類： SRAM
英文描述： 4M X 9 QDR SRAM, PBGA165
封裝： 15 X 17 MM, 1 MM PITCH, LEAD FREE, PLASTIC, LBGA-165
文件頁數(shù)： 7/26頁
文件大?。?/td> 341K
代理商： R1Q2A3609BBG-50RB
R1Q2A3636B/R1Q2A3618B/R1Q2A3609B
REJ03C0341-0003 Rev.0.03 Apr. 11, 2008
Page 15 of 24
AC Characteristics
(Ta = 0 to +70
°C, VDD = 1.8V ± 0.1V)
40
50
60
Parameter
Symbol
Min
Max
Min
Max
Min
Max
Unit
Notes
Average clock cycle time
(K, /K, C, /C)
tKHKH
4.00
8.40
5.00
8.40
6.00
8.40
ns
Clock phase jitter
(K, /K, C, /C)
tKC var
0.20
0.20
0.20
ns
3
Clock high time
(K, /K, C, /C)
tKHKL
1.60
2.00
2.40
ns
Clock low time
(K, /K, C, /C)
tKLKH
1.60
2.00
2.40
ns
Clock to /clock
(K to /K, C to /C)
tKH/KH
1.80
2.20
2.70
ns
/Clock to clock
(/K to K, /C to C)
t/KHKH
1.80
2.20
2.70
ns
Clock to data clock
(K to C, /K to /C)
tKHCH
0
1.10
0
1.60
0
2.10
ns
DLL lock time (K, C)
tKC lock
1,024
1,024
1,024
Cycle
2
K static to DLL reset
tKC reset
30
30
30
ns
7
C, /C high to output valid
tCHQV
0.45
0.45
0.50
ns
C, /C high to output hold
tCHQX
0.45
0.45
0.50
ns
C, /C high to echo clock valid
tCHCQV
0.45
0.45
0.50
ns
C, /C high to echo clock hold
tCHCQX
0.45
0.45
0.50
ns
CQ, /CQ high to output valid
tCQHQV
0.30
0.35
0.40
ns
4, 7
CQ, /CQ high to output hold
tCQHQX
0.30
0.35
0.40
ns
4, 7
C, /C high to output high-Z
tCHQZ
0.45
0.45
0.50
ns
5
C, /C high to output low-Z
tCHQX1
0.45
0.45
0.50
ns
5
Address valid to K, /K rising
edge
tAVKH
0.35
0.40
0.50
ns
1
Control inputs valid to K rising
edge
tIVKH
0.35
0.40
0.50
ns
1
Data-in valid to K, /K rising edge
tDVKH
0.35
0.40
0.50
ns
1
K, /K rising edge to address hold
tKHAX
0.35
0.40
0.50
ns
1
K, /K rising edge to control
inputs hold
tKHIX
0.35
0.40
0.50
ns
1
K, /K rising edge to data-in hold
tKHDX
0.35
0.40
0.50
ns
1
Notes: 1. This is a synchronous device. All addresses, data and control lines must meet the specified setup and hold
times for all latching clock edges.
2. VDD slew rate must be less than 0.1 V DC per 50 ns for DLL lock retention. DLL lock time begins once VDD
and input clock are stable. It is recommended that the device is kept inactive during these cycles.
3. Clock phase jitter is the variance from clock rising edge to the next expected clock rising edge.
4. Echo clock is very tightly controlled to data valid / data hold. By design, there is a ±0.1 ns variation from echo
clock to data. The datasheet parameters reflect tester guardbands and test setup variations.
5. Transitions are measured ±100 mV from steady-state voltage.
6. At any given voltage and temperature tCHQZ is less than tCHQX1 and tCHQZ less than tCHQV.
7. These parameters are sampled.
Remarks:
1. Test conditions as specified with the output loading as shown in AC Test Conditions unless otherwise noted.
2. Control input signals may not be operated with pulse widths less than tKHKL (min).
3. If C, /C are tied high, K, /K become the references for C, /C timing parameters.
4. VDDQ is +1.5 V DC.
5. Control signals are /R, /W, /BW, /BW0, /BW1, /BW2 and /BW3.
BWn signals must operate at the same timing as Data in.
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