參數(shù)資料
型號: R1Q2A3609BBG-50RB
元件分類: SRAM
英文描述: 4M X 9 QDR SRAM, PBGA165
封裝: 15 X 17 MM, 1 MM PITCH, LEAD FREE, PLASTIC, LBGA-165
文件頁數(shù): 6/26頁
文件大?。?/td> 341K
代理商: R1Q2A3609BBG-50RB
R1Q2A3636B/R1Q2A3618B/R1Q2A3609B
REJ03C0341-0003 Rev.0.03 Apr. 11, 2008
Page 14 of 24
Output waveform
VDDQ /2
Test points
VDDQ /2
Output load condition
50
0.75 V
ZQ
Q
VREF
250
Z0 = 50
SRAM
VDDQ /2
AC Operating Conditions
Parameter
Symbol
Min
Typ
Max
Unit
Notes
Input high voltage
VIH (AC)
VREF + 0.2
V
1, 2, 3, 4
Input low voltage
VIL (AC)
VREF
0.2
V
1, 2, 3, 4
Notes: 1. All voltages referenced to VSS (GND).
2. These conditions are for AC functions only, not for AC parameter test.
3. Overshoot: VIH (AC)
≤ VDDQ + 0.5 V for t ≤ tKHKH/2
Undershoot: VIL (AC)
≥ 0.5 V for t ≤ tKHKH/2
Power-up: VIH
≤ VDDQ + 0.3 V and VDD ≤ 1.7 V and VDDQ ≤ 1.4 V for t ≤ 200 ms
During normal operation, VDDQ must not exceed VDD. Control input signals may not have pulse widths less
than tKHKL (min) or operate at cycle rates less than tKHKH (min).
4. To maintain a valid level, the transitioning edge of the input must:
a. Sustain a constant slew rate from the current AC level through the target AC level, VIL (AC) or VIH (AC).
b. Reach at least the target AC level.
c. After the AC target level is reached, continue to maintain at least the target DC level, VIL (DC) or VIH (DC).
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