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參數(shù)資料
| 型號： | R1Q2A3609BBG-50RB |
| 元件分類： | SRAM |
| 英文描述： | 4M X 9 QDR SRAM, PBGA165 |
| 封裝： | 15 X 17 MM, 1 MM PITCH, LEAD FREE, PLASTIC, LBGA-165 |
| 文件頁數(shù)： | 3/26頁 |
| 文件大小： | 341K |
| 代理商： | R1Q2A3609BBG-50RB |
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R1Q2A3636B/R1Q2A3618B/R1Q2A3609B
REJ03C0341-0003 Rev.0.03 Apr. 11, 2008
Page 11 of 24
Bus Cycle State Diagram
Read Port NOP
RInit = 0
Read Double
Load New
Read Address
Power Up
/R = H
Write Port NOP
/W = H
Supply voltage
provided
Supply voltage
provided
/R = L
Always
/R = L
/R = H
Write Double
at /K
↑
Load New
Write Address
at /K
↑
/W = L
Always
/W = L
/W = H
Notes: 1. The address is concatenated with one additional internal LSB to facilitate burst operation. The address order
is always fixed as: xxx…xxx+0, xxx…xxx+1.
Bus cycle is terminated at the end of this sequence (burst count = 2).
2. Read and write state machines can be active simultaneously.
3. State machine control timing sequence is controlled by K.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| R1Q2A3609BBG-60R | 制造商:RENESAS 制造商全稱:Renesas Technology Corp 功能描述:36-Mbit QDR?II SRAM 2-word Burst |
| R1Q2A3609RBG-40RB0 | 制造商:RENESAS 制造商全稱:Renesas Technology Corp 功能描述:36-Mbit QDR?II SRAM 2-word Burst |
| R1Q2A3609RBG-40RS0 | 制造商:RENESAS 制造商全稱:Renesas Technology Corp 功能描述:36-Mbit QDR?II SRAM 2-word Burst |
| R1Q2A3609RBG-40RT0 | 制造商:RENESAS 制造商全稱:Renesas Technology Corp 功能描述:36-Mbit QDR?II SRAM 2-word Burst |
| R1Q2A3609RBG-50RB0 | 制造商:RENESAS 制造商全稱:Renesas Technology Corp 功能描述:36-Mbit QDR?II SRAM 2-word Burst |
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