Though the V
參數(shù)資料
型號: PIC18F46J50-I/PT
廠商: Microchip Technology
文件頁數(shù): 39/164頁
文件大?。?/td> 0K
描述: IC PIC MCU FLASH 64KB 44-TQFP
產(chǎn)品培訓模塊: XLP Deep Sleep Mode
PIC18 J Series MCU Overview
PIC18F MPLAB® Starter Kit
8-bit PIC® Microcontroller Portfolio
標準包裝: 160
系列: PIC® XLP™ 18F
核心處理器: PIC
芯體尺寸: 8-位
速度: 48MHz
連通性: I²C,SPI,UART/USART,USB
外圍設備: 欠壓檢測/復位,DMA,POR,PWM,WDT
輸入/輸出數(shù): 34
程序存儲器容量: 64KB(32K x 16)
程序存儲器類型: 閃存
RAM 容量: 3.8K x 8
電壓 - 電源 (Vcc/Vdd): 2.15 V ~ 3.6 V
數(shù)據(jù)轉(zhuǎn)換器: A/D 13x10b
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 85°C
封裝/外殼: 44-TQFP
包裝: 托盤
產(chǎn)品目錄頁面: 657 (CN2011-ZH PDF)
配用: AC164330-ND - MODULE SKT FOR 44TQFP 18F45J10
2011 Microchip Technology Inc.
DS39931D-page 133
PIC18F46J50 FAMILY
10.1.3
INTERFACING TO A 5V SYSTEM
Though the VDDMAX of the PIC18F46J50 family is 3.6V,
these devices are still capable of interfacing with 5V
systems, even if the VIH of the target system is above
3.6V. This is accomplished by adding a pull-up resistor
to the port pin (Figure 10-2), clearing the LAT bit for that
pin and manipulating the corresponding TRIS bit
(Figure 10-1) to either allow the line to be pulled high,
or to drive the pin low. Only port pins that are tolerant of
voltages up to 5.5V can be used for this type of
).
FIGURE 10-2:
+5V SYSTEM HARDWARE
INTERFACE
EXAMPLE 10-1:
COMMUNICATING WITH
THE +5V SYSTEM
10.1.4
OPEN-DRAIN OUTPUTS
The output pins for several peripherals are also
equipped with a configurable open-drain output option.
This allows the peripherals to communicate with
external digital logic, operating at a higher voltage
level, without the use of level translators.
The open-drain option is implemented on port pins
specifically associated with the data and clock outputs
of the EUSARTs, the MSSP modules (in SPI mode) and
the ECCP modules. It is selectively enabled by setting
the open-drain control bit for the corresponding module
in the ODCON registers (Register 10-1, Register 10-2
and Register 10-3). Their configuration is discussed in
more detail with the individual port where these
peripherals are multiplexed. Output functions that are
routed through the PPS module may also use the
open-drain option. The open-drain functionality will
follow the I/O pin assignment in the PPS module.
When the open-drain option is required, the output pin
must also be tied through an external pull-up resistor,
provided by the user, to a higher voltage level, up to
5.5V (Figure 10-3). When a digital logic high signal is
output, it is pulled up to the higher voltage level.
FIGURE 10-3:
USING THE OPEN-DRAIN
OUTPUT (USART SHOWN
AS EXAMPLE)
10.1.5
TTL INPUT BUFFER OPTION
Many of the digital I/O ports use Schmitt Trigger (ST)
input buffers. While this form of buffering works well
with many types of input, some applications may
require TTL level signals to interface with external logic
devices. This is particularly true for the Parallel Master
Port (PMP), which is likely to be interfaced to TTL level
logic or memory devices.
The inputs for the PMP can be optionally configured for
TTL buffers with the PMPTTL bit in the PADCFG1 reg-
ister (Register 10-4). Setting this bit configures all data
and control input pins for the PMP to use TTL buffers.
By default, these PMP inputs use the port’s ST buffers.
RD7
+5V Device
+5V
PIC18F46J50
BCF
LATD, 7
; set up LAT register so
; changing TRIS bit will
; drive line low
BCF
TRISD, 7
; send a 0 to the 5V system
BSF
TRISD, 7
; send a 1 to the 5V system
TXX
+5V
(at logic ‘1’)
3.3V
VDD
5V
PIC18F46J50
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