參數(shù)資料
型號： PIC18F46J50-I/PT
廠商： Microchip Technology
文件頁數(shù)： 120/164頁
文件大小： 0K
描述： IC PIC MCU FLASH 64KB 44-TQFP
產(chǎn)品培訓(xùn)模塊： XLP Deep Sleep Mode
PIC18 J Series MCU Overview
PIC18F MPLAB® Starter Kit
8-bit PIC® Microcontroller Portfolio
標準包裝： 160
系列： PIC® XLP™ 18F
核心處理器： PIC
芯體尺寸： 8-位
速度： 48MHz
連通性： I²C，SPI，UART/USART，USB
外圍設(shè)備： 欠壓檢測/復(fù)位，DMA，POR，PWM，WDT
輸入/輸出數(shù)： 34
程序存儲器容量： 64KB（32K x 16）
程序存儲器類型： 閃存
RAM 容量： 3.8K x 8
電壓 - 電源 (Vcc/Vdd)： 2.15 V ~ 3.6 V
數(shù)據(jù)轉(zhuǎn)換器： A/D 13x10b
振蕩器型： 內(nèi)部
工作溫度： -40°C ~ 85°C
封裝/外殼： 44-TQFP
包裝： 托盤
產(chǎn)品目錄頁面： 657 (CN2011-ZH PDF)
配用： AC164330-ND - MODULE SKT FOR 44TQFP 18F45J10
2011 Microchip Technology Inc.
DS39931D-page 59
PIC18F46J50 FAMILY
REGISTER 4-5:
DSWAKEH: DEEP SLEEP WAKE HIGH BYTE REGISTER (BANKED F4Bh)
U-0
R/W-0
—
—DSINT0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 7-1
Unimplemented:
Read as ‘0’
bit 0
DSINT0:
Interrupt-on-Change bit
1
= Interrupt-on-change was asserted during Deep Sleep
0
= Interrupt-on-change was not asserted during Deep Sleep
REGISTER 4-6:
DSWAKEL: DEEP SLEEP WAKE LOW BYTE REGISTER (BANKED F4Ah)
R/W-0
U-0
R/W-0
U-0
R/W-1
DSFLT
—
DSULP
DSWDT
DSRTC
DSMCLR
—
DSPOR
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 7
DSFLT:
Deep Sleep Fault Detected bit
1
= A Deep Sleep Fault was detected during Deep Sleep
0
= A Deep Sleep Fault was not detected during Deep Sleep
bit 6
Unimplemented:
Read as ‘0’
bit 5
DSULP:
Ultra Low-Power Wake-up Status bit
1
= An Ultra Low-Power Wake-up event occurred during Deep Sleep
0
= An Ultra Low-Power Wake-up event did not occur during Deep Sleep
bit 4
DSWDT:
Deep Sleep Watchdog Timer Time-out bit
1
= The Deep Sleep Watchdog Timer timed out during Deep Sleep
0
= The Deep Sleep Watchdog Timer did not time out during Deep Sleep
bit 3
DSRTC:
Real-Time Clock and Calendar Alarm bit
1
= The Real-Time Clock/Calendar triggered an alarm during Deep Sleep
0
= The Real-Time Clock /Calendar did not trigger an alarm during Deep Sleep
bit 2
DSMCLR:
MCLR Event bit
1
= The MCLR pin was asserted during Deep Sleep
0
= The MCLR pin was not asserted during Deep Sleep
bit 1
Unimplemented:
Read as ‘0’
bit 0
DSPOR:
Power-on Reset Event bit
1
= The VDD supply POR circuit was active and a POR event was detected(1)
0
= The VDD supply POR circuit was not active, or was active, but did not detect a POR event
Note 1:
Unlike the other bits in this register, this bit can be set outside of Deep Sleep.
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