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參數資料
| 型號： | PIC18F46J50-I/PT |
| 廠商： | Microchip Technology |
| 文件頁數： | 37/164頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC PIC MCU FLASH 64KB 44-TQFP |
| 產品培訓模塊： | XLP Deep Sleep Mode PIC18 J Series MCU Overview PIC18F MPLAB® Starter Kit 8-bit PIC® Microcontroller Portfolio |
| 標準包裝： | 160 |
| 系列： | PIC® XLP™ 18F |
| 核心處理器： | PIC |
| 芯體尺寸： | 8-位 |
| 速度： | 48MHz |
| 連通性： | I²C，SPI，UART/USART，USB |
| 外圍設備： | 欠壓檢測/復位，DMA，POR，PWM，WDT |
| 輸入/輸出數： | 34 |
| 程序存儲器容量： | 64KB（32K x 16） |
| 程序存儲器類型： | 閃存 |
| RAM 容量： | 3.8K x 8 |
| 電壓 - 電源 (Vcc/Vdd)： | 2.15 V ~ 3.6 V |
| 數據轉換器： | A/D 13x10b |
| 振蕩器型： | 內部 |
| 工作溫度： | -40°C ~ 85°C |
| 封裝/外殼： | 44-TQFP |
| 包裝： | 托盤 |
| 產品目錄頁面： | 657 (CN2011-ZH PDF) |
| 配用： | AC164330-ND - MODULE SKT FOR 44TQFP 18F45J10 |
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2011 Microchip Technology Inc.
DS39931D-page 131
PIC18F46J50 FAMILY
10.0
I/O PORTS
Depending on the device selected and features
enabled, there are up to five ports available. Some pins
of the I/O ports are multiplexed with an alternate
function from the peripheral features on the device. In
general, when a peripheral is enabled, that pin may not
be used as a general purpose I/O pin.
Each port has three registers for its operation. These
registers are:
TRIS register (Data Direction register)
PORT register (reads the levels on the pins of the
device)
LAT register (Data Latch)
Pins that are multiplexed with analog functionality (ANx
pins) also have ANCON register bits associated with
them.
The TRISx registers control which pins should be con-
figured as digital outputs (output buffer enabled) and
which pins should be left high-impedance. Writing ‘0’ to
a TRIS bit configures the specified pin as a digital out-
put. Writing a ‘1’ to a TRIS bit disables the output driver,
so the pin can be used as a digital or analog input. This
can be easily remembered by observing that ‘0’ is sim-
ilar to the letter, O (as in Output), and that ‘1’ is similar
to the letter, I (as in Input).
The PORTx registers can be used to read the logic level
externally presented on pins that have been configured
as digital inputs. If a pin is configured as a digital input,
the corresponding port bit will be read as ‘1’ if the exter-
nally applied voltage is greater than the VIH level for that
pin. If the externally applied voltage is below VIL, then
the PORTx bit will read as ‘0’. If the I/O pin is multiplexed
with analog functionality (an ANx pin), then the corre-
sponding PCFG bit, in the appropriate ANCONx register,
must also be set, in order to correctly read the externally
applied voltage on the pin. See the following information
regarding the ANCONx registers.
If the application firmware writes to a PORTx register,
this will cause the corresponding LATx register to be
updated. It is usually not recommended to perform
read-modify-write instructions (ex: BTG, BSF, BCF) on a
PORTx register. If the application firmware wishes to
change the output state of a pin that has been
configured as a digital output (TRIS bit = 0), it is
recommended that the firmware use the corresponding
LATx register instead.
The LATx registers hold the digital value that is output
onto a pin when the pin has been configured as a digital
output (TRIS bit = 0). Writing a ‘1’ to the LATx bit will
drive the output pin to the logic high output state.
Similarly, writing a ‘0’ to the LAT bit will drive the output
pin to a logic low output state. It is safe to perform all
types of read, write and read-modify-write instructions
on the LATx registers.
The ANCONx registers are used to configure pins with
ANx analog functionality for either Digital Input or Analog
Input mode. Setting a PCFG bit in an ANCONx register
enables the digital input buffer, allowing reads from the
PORTx register to correctly reflect the externally applied
voltage on the digital input pin. If the PCFG bit is clear,
the digital input buffer is disabled, to eliminate CMOS
input buffer cross conduction currents, when a mid-VDD
scale analog voltage is applied to the pin. This allows
analog input voltages (between VDD and VSS) to be
applied to the pin without increasing the current con-
sumption of the device. If the appropriate PCFG bit in the
ANCONx register is not set, this will cause the PORTx
register bit for that pin to read as ‘0’, regardless of the
actually applied external voltage.
At power-up, the default state of the ANCONx registers
is to configure the ANx pins for Analog mode (digital
input buffer off). Therefore, to use ANx pins as digital
inputs, the application firmware must first update the
ANCONx register(s). See Section 21.0 “10-bit Ana-
for more
details regarding the ANCONx registers.
Figure 10-1 displays a simplified model of a generic I/O
port, without the interfaces to other peripherals.
FIGURE 10-1:
GENERIC I/O PORT
OPERATION
Data
Bus
WR LAT
WR TRIS
RD PORT
Data Latch
TRIS Latch
RD TRIS
Input
Buffer
I/O Pin(1)
Q
D
CK
Q
D
CK
EN
QD
EN
RD LAT
or PORT
Note 1:
I/O pins without 5.5V tolerance have diode
protection to VDD and VSS. I/O pins with
5.5V tolerance have diode protection from
Vss.
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