參數(shù)資料
型號: PF38F3050L0YUQ3A
廠商: INTEL CORP
元件分類: 存儲器
英文描述: SPECIALTY MEMORY CIRCUIT, PBGA88
封裝: 8 X 10 MM, 1.20 MM HEIGHT, ROHS COMPLIANT, SCSP-88
文件頁數(shù): 70/70頁
文件大?。?/td> 1193K
代理商: PF38F3050L0YUQ3A
Intel StrataFlash Wireless Memory (L18 SCSP)
August 2006
Datasheet
Order Number: 314476-001
9
768-Mbit LQ Family with Synchronous PSRAM
1.1
Nomenclature
1.8 Volt Core VCC (memory subsystem die core) voltage range of 1.7 V – 1.95 V.
1.8 Volt I/O VCCQ (memory subsystem I/O) voltage range of 1.7 V – 1.95 V.
ADMux I/O
Address-Data Multiplex I/O interface, where the lower sixteen (16)
addresses are multiplexed on the data pins (DQ[15:0]) during any
address cycle.
Asserted
Signal with logical voltage level VIL, or enabled.
Block
Group of cells, bits, bytes, or words within the flash memory array
that get erased with one erase instruction.
Deasserted
Signal with logical voltage level VIH or disabled.
Device
A specific memory type or stacked flash and xRAM memory density
configuration combination within a memory subsystem product family.
Die
Individual flash or xRAM die used in a stacked package memory
device.
High-Z
High Impedance.
Low-Z
Signal is Driven on the bus.
Non-Array
Reads
Flash reads which return flash Device Identifier, CFI Query, Protection
Register, and Status Register information.
Non-Mux I/O Traditional parallel flash interface where address are not multiplex
onto the data pins. All address and data pins are unique.
Partition
A group of flash blocks that shares common status register read state.
Program
An operation to Write data to the flash array or xRAM.
Write
Bus cycle operation at the inputs of the flash or xRAM die, in which a
command or data are sent to the flash array or xRAM.
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