參數(shù)資料
型號(hào): PF38F3050L0YUQ3A
廠商: INTEL CORP
元件分類: 存儲(chǔ)器
英文描述: SPECIALTY MEMORY CIRCUIT, PBGA88
封裝: 8 X 10 MM, 1.20 MM HEIGHT, ROHS COMPLIANT, SCSP-88
文件頁(yè)數(shù): 51/70頁(yè)
文件大?。?/td> 1193K
代理商: PF38F3050L0YUQ3A
Intel StrataFlash Wireless Memory (L18 SCSP)
August 2006
Datasheet
Order Number: 314476-001
55
768-Mbit LQ Family with Synchronous PSRAM
Table 19. Bus Control Register Description
B
CR Bit
NAME
Description
22:20
Reserved
Reserved bits should be set to ‘0’ during set control register
commands
19:18
Register Select
10 = Select BCR
17:16
Reserved
Reserved bits should be set to ‘0’ during set control register
commands
15
Operating Mode
0 = Synchronous Burst Mode
1 = Asynchronous Mode (Default)
14
Initial Latency
0 = Variable (Default)
1 = Fixed
13:11
Latency Counter
000 = Code 0 - Reserved
001 = Code 1 - Reserved
010 = Code 2
011 = Code 3 (Default)
100 = Code 4
101 = Code 5
110 = Code 6
111 = Code 7 - Reserved
10
WAIT Polarity
0 = Active Low
1 = Active High (Default)
9
Reserved
Reserved bits should be set to ‘0’ during set control register
commands
8
WAIT Configuration
0 = WAIT asserted during delay
1 = WAIT asserted one data cycle before delay (Default)
7:6
Reserved
Reserved bits should be set to ‘0’ during set control register
commands
5:4
Drive Strength
00 = Full
01 = 1/2 (Default)
10 = 1/4
11 = Reserved
3Burst Wrap
0 = Burst wraps within the burst length
1 = Burst does not wrap (Default)
2:0
Burst Length
000 = Reserved
001 = 4 words
010 = 8 words
011 = 16 words
100 = 32 words
101 = Reserved
110 = Reserved
111 = Continuous Burst (Default)
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