參數(shù)資料
型號(hào)： PF38F3050L0YUQ3A
廠商： INTEL CORP
元件分類： 存儲(chǔ)器
英文描述： SPECIALTY MEMORY CIRCUIT, PBGA88
封裝： 8 X 10 MM, 1.20 MM HEIGHT, ROHS COMPLIANT, SCSP-88
文件頁(yè)數(shù)： 52/70頁(yè)
文件大?。?/td> 1193K
代理商： PF38F3050L0YUQ3A
768-Mbit LQ Family with Synchronous PSRAM
Intel StrataFlash Wireless Memory (L18 SCSP)
Datasheet
August 2006
56
Order Number: 314476-001
768-Mbit LQ Family with Synchronous PSRAM
12.2.1.1
PSRAM BCR Operating Mode
The PSRAM supports three different interface access protocols:
SRAM-type protocol with asynchronous read and write accesses
NOR-Flash-type protocol with synchronous read and asynchronous write accesses
FULL SYNCHRONOUS mode with synchronous read and synchronous write accesses
Operating the PSRAM in synchronous mode maximizes bandwidth. The NOR-Flash type
mode is the recommended mode for legacy systems which are not able to run the
synchronous write protocol. The Operating Mode bit BCR15 defines whether the device
is operating in synchronous (fully or partially) mode or asynchronous mode.
When BCR15 is set low, the mode of write operation, NOR-flash or Full synchronous, is
adaptively detected by detecting a rising clock edge during ADV# valid. If a rising clock
edge occurs within ADV# valid, Full synchronous write is detected. If there is no rising
clock edge then NOR-Flash write is detected and CE# must go high when transitioning
from asynchronous to synchronous operation or when transitioning from synchronous
to asynchronous operation..
When BCR15 is set high, the SRAM-type mode of operation is selected.
Warning:
When operating the PSRAM as an ADMux I/O interface by connecting the lower sixteen
(16) addresses, A[15:0], to the data pins, ADV# must be de-asserted during any data
phase cycle.
12.2.1.2
PSRAM Initial Latency BCR Bit
The PSRAM latency is related to the number of clock cycles from the burst-init
command to be either 1st valid data output (read burst) or 1st valid data input (burst
write.) In Fixed Latency mode, the number of clock cycles from bust-init command to
valid data is always fixed as defined by the Latency Counter setting in the BCR. In
Variable Latency mode, the number of clock cycles from bust-init command to valid
data output (read burst) is variable depending on internal device operation. The
minimum latency in Variable Latency mode is defined by the Latency Counter setting in
the BCR. Additional WAIT cycles may be added in Variable Latency mode if the burst-
init Read command collides with an on-going internal refresh. Additional WAIT cycles
are not added for burst-init Write commands in Variable Latency mode.
12.2.1.3
PSRAM Latency Counter BCR Bit
The latency counter defines the number of clock cycles that pass before the first output
data is valid (read burst) or before the first input data is valid (read burst.) Each
Latency Code setting has an associate maximum PSRAM clock frequency. In the case of
Variable Latency the first access delay might be extended by additional wait cycles in
case the burst read access collides with an ongoing self-refresh operation. The allowed
values of the Latency Counter also depend on the Initial Latency setting in BCR.
Table 20. Optional PSRAM BCR Latency Counter Settings in Variable Latency
Latency
Counter
PSRAM
010
Code 2; Max 54 MHz
011
Code 3; Max 80 MHz
Others
Reserved
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