參數(shù)資料
型號: PF38F3050L0YUQ3A
廠商: INTEL CORP
元件分類: 存儲器
英文描述: SPECIALTY MEMORY CIRCUIT, PBGA88
封裝: 8 X 10 MM, 1.20 MM HEIGHT, ROHS COMPLIANT, SCSP-88
文件頁數(shù): 57/70頁
文件大?。?/td> 1193K
代理商: PF38F3050L0YUQ3A
768-Mbit LQ Family with Synchronous PSRAM
Intel StrataFlash Wireless Memory (L18 SCSP)
Datasheet
August 2006
60
Order Number: 314476-001
768-Mbit LQ Family with Synchronous PSRAM
12.2.2.1
PSRAM Page Mode RCR Bit
In asynchronous (SRAM) mode, the user has the option to enable page mode. Page
mode applies only to asynchronous read operations and has no impact on
asynchronous write operations. In synchronous and NOR-Flash modes, the page mode
setting has no impact on PSRAM operation. The maximum page length is 16 words, so
A[3:0] is regarded as the page address.
Warning:
When operating the PSRAM as an ADMux I/O interface by connecting the lower sixteen
(16) addresses, A[15:0], to the data pins, Page-Mode operation cannot be used.
12.2.2.2
PSRAM Deep-Power Down RCR Bit
To put the device in deep power down mode the DPD control bit must be set low
(RCR4 =0.) All internal voltage generators inside the PSRAM are switched off and the
internal self-refresh is stopped. This means that all stored memory information will be
lost by entering DPD. Only the register values of BCR, and RCR remain valid during
DPD.
12.2.2.2.1 PSRAM Deep-Power Down Entry
To enter deep power down, RCR4 is set low, CE# is then pulled high and is maintained
high for the entire time duration that Deep Power Down mode is desired. To insure
proper operation, once CE# is pulled high, it should be maintained high for minimum of
150 s before beginning the Deep Power Down Exit sequence.
12.2.2.2.2 PSRAM Deep-Power Down Exit
To exit the deep power down mode the CE# must go low for minimum 10 s, followed
by a guard time of at least 150 s where CE# must be maintained high. Once deep
power down is exited, the DPD control bit RCR4 is automatically reset to 1. All other
Control Register contents are unchanged.
Figure 32. Deep Power Down Exit Timing
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