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參數(shù)資料
| 型號： | PF38F3050L0YUQ3A |
| 廠商： | INTEL CORP |
| 元件分類： | 存儲器 |
| 英文描述： | SPECIALTY MEMORY CIRCUIT, PBGA88 |
| 封裝： | 8 X 10 MM, 1.20 MM HEIGHT, ROHS COMPLIANT, SCSP-88 |
| 文件頁數(shù)： | 24/70頁 |
| 文件大小： | 1193K |
| 代理商： | PF38F3050L0YUQ3A |
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768-Mbit LQ Family with Synchronous PSRAM
Intel StrataFlash Wireless Memory (L18 SCSP)
Datasheet
August 2006
30
Order Number: 314476-001
768-Mbit LQ Family with Synchronous PSRAM
5.3
Device Power-Up/Down
5.3.1
Flash Power and Reset Specifications
Refer to the Intel StrataFlash Wireless Memory (L18 SCSP) Datasheet (order
number: Non-Mux I/O doc #251902 and ADMux I/O doc #313295) for detailed
information.
5.3.2
PSRAM Power-Up Sequence and Initialization
The power-on and initialization sequence ensures that the device is properly
preconditioned to operate as expected. Like conventional DRAMs, the PSRAM must be
powered up and initialized in a predefined manner. VCC and VCCQ must be applied at
the same time to the specified voltage while the input signals are held in a deselected
state (CS# = High).
After power on, an initial pause of 150 s is required prior to the control register access
or normal operation. Failure to follow these steps may lead to unpredictable behavior.
The default operation mode after power up is the asynchronous (SRAM) mode.
Figure 10. PSRAM Timing Waveform for Power-Up Sequence
Device ready for normal operation
Device Initialization
P-Vcc MIN
P-VCC/
VCCQ
P-CS#
tPU >= 150 s
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