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OctalLIU
TM
PEF 22508 E
Functional Description
Data Sheet
52
Rev. 1.0, 2005-06-02
Figure 15
Block Diagram of Test Access Port and Boundary Scan
After switching on the device (power-on), a reset signal has to be applied to TRS, which forces the TAP controller
into test logic reset state.
For normal operation without boundary scan access, the boundary reset pin TRS can be tied to the device reset
pin RES.
The boundary length is 247.
If no boundary scan operation is used, TRS has to be connected to RST or V
SS. TMS, TCK and TDI do not need
to be connected since pull-up transistors ensure high input levels in this case.
Test handling (boundary scan operation) is performed using the pins TCK (Test Clock), TMS (Test Mode Select),
TDI (Test Data Input) and TDO (Test Data Output) when the TAP controller is not in its reset state, that means
TRS is connected to V
DD or it remains unconnected due to its internal pull up. Test data at TDI is loaded with a
clock signal connected to TCK. "1" or "0" on TMS causes a transition from one controller state to another; constant
"1" on TMS leads to normal operation of the chip.
An input pin (I) uses one boundary scan cell (data in), an output pin (O) uses two cells (data out and enable) and
an I/O-pin (I/O) uses three cells (data in, data out and enable). Note that most functional output and input pins of
the OctalLIU
TM are tested as I/O pins in boundary scan, hence using three cells.
The desired test mode is selected by serially loading a 8-bit instruction code into the instruction register through
TDI (LSB first), see Table 10. The test modes are:
EXTEST
Extest is used to examine the interconnection of the devices on the board. In this test mode at first all input pins
capture the current level on the corresponding external interconnection line, whereas all output pins are held at
constant values ("0" or "1"). Then the contents of the boundary scan is shifted to TDO. At the same time the next
scan vector is loaded from TDI. Subsequently all output pins are updated according to the new boundary scan
contents and all input pins again capture the current external level afterwards, and so on.
F0115
TRS
TCK
TMS
TDI
TDO
clock
test
control
data in
enable
data
out
Clock
Generation
Reset
TAP Controller
finite state machine
instruction register
test signal generator
TAP controller reset
Id
en
tifi
ca
tio
nR
eg
is
te
r
(3
2bi
ts
)
control
bus
B
oundar
yS
can
(n
b
its
)
1
2
n
BD data in
BD data out
ID data out