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Data Sheet
45
Rev. 1.0, 2005-06-02
OctalLIU
TM
PEF 22508 E
Functional Description
Figure 6
SCI Interface Application with Point To Point Connections
Figure 7
SCI Interface Application with Multipoint To Multipoint Connection
The following configurations of the SCI interface of the OctalLIU
TM can be set by the micro controller by a write
command into the SCI configuration register (control bits 10
B, see Table 8, SCI register address is 0000H, see Half duplex/full duplex (reset value: Half duplex), bit DUP.
OpenDrain/push-pull (configuration of output pin to openDrain/push-pull is in general independent of the
duplex mode and must be set appropriately in application) (reset value: open Drain), bit PP.
CRC for transmit and receive on/off (reset value: off), bit CRC_EN.
Automatic acknowledgement of CMD messages on/off (reset value: off), bit ACK_EN.
Clock edge rising/falling (reset value: falling), bit CLK_POL.
Clock gating (reset value: off), bit CLK_GAT.
The following SCI configurations are fixed and cannot be set by the micro controller:
Interrupt feature is disabled, bit INT_EN = 0
B.
Arbitration always made with LAPD (only SCI applications like in Figure 6 and Figure 7 are possible), bit ARB
= 0
B.
The maximum possible SCI clock frequency is 6 MHz for point to point applications (full duplex) and about 2 MHz
for multipoint to multipoint applications, dependent on the electrical capacity of the bus lines of the PCB.
Figure 8 shows the message structure of the OctalLIU
TM. The SCI interface uses HDLC frames for
communication. The HDLC flags mark beginning and end of all messages.
Microprocessor
or
Interworking
Device
IM(1:0)
TxData
RxData
Clk
TxData
RxData
Clk
TxData
RxData
Clk
OctalLIU
SCI_TXD
SCI_RXD
PP
OctalLIU
OctalLIU-Interfaces_2
Micro-processor
or
Interworking
Device
IM(1:0)
Clk
OctalLIU_SCI_halfduplex
A(5:0)
SCI_RXD
oD
OctalLIU
SCI_TXD
Data
OctalLIU