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參數(shù)資料
| 型號(hào)： | PDI1394L21 |
| 廠商： | NXP Semiconductors N.V. |
| 英文描述： | Full Duplex AV Link Layer Ccontroller(全雙工AV鏈接層控制器) |
| 中文描述： | 全雙工鏈路層Ccontroller影音（全雙工視聽鏈接層控制器） |
| 文件頁數(shù)： | 9/54頁 |
| 文件大?。?/td> | 242K |
| 代理商： | PDI1394L21 |
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Philips Semiconductors
Preliminary specification
PDI1394L21
1394 full duplex AV link layer controller
2000 Jun 06
9
11.1
Buffer Memory Sizes
BUFFER MEMORY
SIZE
(Quadlets)
64
128
64
64
1024
1024
Asynchronous Receive Response FIFO
Asynchronous Receive Request FIFO
Asynchronous Transmit Response FIFO
Asynchronous Transmit Request FIFO
Isochronous (AV) Transmit Buffer
Isochronous (AV) Receive Buffer
12.0
12.1
The PDI1394L21 is an IEEE 1394–1995 compliant link layer controller. It provides a direct interface between a 1394 bus and various MPEG–2
and DVC codecs. Via this interface, the AV Link maps and unmaps these AV datastreams from these codecs onto 1394 isochronous bus
packets. The AV Link also provides an 8051 compatible microcontroller interface for an attached host controller. Through the host interface port,
the host controller can configure the AV layer for transmission or reception of AV datastreams. The host interface port also allows the host
controller to transmit and receive 1394 asynchronous data packets.
12.2
AV interface and AV layer
The AV interface and AV layer allow AV packets to be transmitted from one node to another. The AV transmitter and receiver within the AV layer
perform all the functions required to pack and unpack AV packet data for transfer over a 1394 network. Once the AV layer is properly configured
for operation, no further host controller service should be required. The operation of the AV layer is full-duplex, i.e., the AV layer can receive and
transmit AV packets at the same time.
FUNCTIONAL DESCRIPTION
Overview
12.2.1
The AV Link provides an 8 bit data path to the AV layer. The 8 bit data path is designed with associated clock and control signals to be
compatible with various MPEG–2 and DVC codecs.
The AV interface port buffer, if so programmed, can time stamp incoming AV packets. The AV packet data is stored in the embedded memory
buffer, along with its time stamp information. After the AV packet has been written into the AV layer, the AV layer creates an isochronous bus
packet with the appropriate CIP header. The bus packet along with the CIP header is transferred over the appropriate isochronous
channel/packet. The size and configuration of isochronous data packet payload transmitted is determined by the AV layer’s configuration
registers accessible through the host interface.
The AV Interface
The AV interface port waits for the assertion for AVxVALID and AVxSYNC.
Note:
Do not assert AVxSYNC without AVxVALID. AVxSYNC is
aligned with the rising edge of AVxCLK and the first byte of data on AVxDATA[7:0]. The duration of AVxSYNC is one AVxCLK cycle. AVxSYNC
signals the AV layer that the transfer of an AV packet has begun. At the time the AVxSYNC is asserted, the AV layer creates a new time stamp
in the buffer memory. (This only happens if so configured. The DVC format does not use these time stamps). The time stamp is then transmitted
as part of the source packet header. This allows the AV receiver to provide the AV packet for output at the appropriate time. Only one AVSYNC
pulse is allowed per application packet; if additional sync pulses are presented before the full packet is inputted, a new packet will be started
and the previously inputted packet data will be discarded (and not transmitted) in conjunction with the input error interrupt bit (INPERR, bit 3 of
register 0x02C) being set to flag the error.
When the DV video is enabled (via the format code of the CIP header), the frame synchronization signal AVxFSYNC is time stamped and
placed in the SYT field. The default timestamp value is 3 cycle times (duration of 125 s each) in the future and is transmitted in the SYT field of
the current CIP header; this value is programmable from 2 to 4 cycle times (see section 13.2.1). On the receiver side, when the SYT stamp
matches the cycle timer register, a pulse is generated on the AVxFSYNC output. The timing for AVxFSYNC is independent of AVxCLK.
12.2.2
The PDI1394L21 is specifically designed to support the IEC61883 International Standard of Digital Interface for Consumer Electronic
Audio/Video Equipment. The IEC specification defines a scheme for mapping various types of AV datastreams onto 1394 isochronous data
packets. The standard also defines a software protocol for managing isochronous connections in a 1394 bus called Connection Management
Protocol (CMP). It also provides a framework for transfer of functional commands, called Function Control Protocol (FCP).
IEC 61883 International Standard
12.2.3
A feature of the IEC61883 International Standard is the definition of Common Isochronous Packet (CIP) headers. These CIP headers contain
information about the source and type of datastream mapped onto the isochronous packets.
The AV Layer supports the use of CIP headers. CIP headers are added to transmitted isochronous data packets at the AV data source. When
receiving isochronous data packets, the AV layer automatically analyzes their CIP headers. The analysis of the CIP headers determines the
method the AV layer uses to unpack the AV data from the isochronous data packets.
CIP Headers
The information contained in the CIP headers is accessible via registers in the host interface.
(See IEC61883 International Standard of Digital Interface for Consumer Electronic Audio/Video Equipment for more details on CIP headers).
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| PDI1394L41 | Content Protection AV Link Layer(內(nèi)容可保護(hù)的AV鏈接層控制器) |
| PDI1394P21 | 3-port Physical Layer Interface(三端口物理層接口) |
| PDI1394P22 | 3-port Physical Layer Interface(三端口物理層接口) |
| PDI1394P24 | 2-port 400 Mbps physical layer interface(2端口 400 Mbps物理層接口) |
| PDI40C1D00 | |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| PDI1394L21BE | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:1394 full duplex AV link layer controller |
| PDI1394L21BP | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:1394 full duplex AV link layer controller |
| PDI1394L40 | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:1394 enhanced AV link layer controller |
| PDI1394L40BE | 制造商:NXP Semiconductors 功能描述:1 CHANNEL(S), 400M BPS, SERIAL COMM CONTROLLER, PQFP144 |
| PDI1394L40BE,518 | 功能描述:視頻 IC 1394 A/V LINK LAYER RoHS:否 制造商:Fairchild Semiconductor 工作電源電壓:5 V 電源電流:80 mA 最大工作溫度:+ 85 C 封裝 / 箱體:TSSOP-28 封裝:Reel |
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