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參數(shù)資料
| 型號： | PDI1394L21 |
| 廠商： | NXP Semiconductors N.V. |
| 英文描述： | Full Duplex AV Link Layer Ccontroller(全雙工AV鏈接層控制器) |
| 中文描述： | 全雙工鏈路層Ccontroller影音（全雙工視聽鏈接層控制器） |
| 文件頁數(shù)： | 29/54頁 |
| 文件大?。?/td> | 242K |
| 代理商： | PDI1394L21 |
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Philips Semiconductors
Preliminary specification
PDI1394L21
1394 full duplex AV link layer controller
2000 Jun 06
29
13.1
Link Control Registers
13.1.1
ID Register (IDREG) – Base Address: 0x000
The ID register is automatically updated by the attached PHY with the proper Node ID after completion of the bus reset.
29 28 272625 24 23 22 212019 18 1716 15 1413 12 11 10 9 8 7 6 5 4 3 2 1 0
SV00915
NODE ID
BUS ID
VERSION CODE
3130
PART CODE
Reset Value 0xFFFF0101
Bit 31..22:
R/W
BUS ID: The 10-bit bus number that is used with the Node ID in the source address for outgoing packets and used to
accept or reject incoming packets. This field reverts to all ‘1’s (0x3FF) upon bus reset.
NODE ID: Used in conjunction with Bus ID in the source address for outgoing packets and used to accept or reject
incoming packets. This register auto-updates with the node ID assigned after the 1394 bus Tree-ID sequence.
PART CODE: “01” designates PDI1394L21.
VERSION CODE: “02” shows this is revision level 2 of this part.
Bit 21..16:
R/W
Bit 15..8:
Bit 7..0:
R
R
13.1.2
The General Link control register is used to program the Link Layer isochronous transceiver, as well as the overall link transceiver. It also
provides general link status.
General Link Control (LNKCTL) – Base Address: 0x004
29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7
6
5 4 3
2 1
0
SV00892
I
R
R
B
C
S
C
C
R
R
T
R
BSYCTRL
ATACK
31 30
T
R
D
L
Reset Value 0x46000002
Bit 31:
R/W
IDValid (IDVALID): When equal to one, the PDI1394L21 accepts the packets addressed to this node. This bit is
automatically set after selfID complete and node ID is updated.
Receive Self ID (RCVSELFID): When asserted, the self-identification packets, generated by each PHY device on the
bus, during bus initialization are received and placed into the asynchronous request queue as a single packet. Bit 30
also enables the reception of PHY configuration packets in the asynchronous request queue.
Busy Control (BSYCTRL): These bits control what busy status the chip returns to incoming packets. The field is
defined below:
000 =
use protocol requested by received packet (either dual phase or single phase)
001 =
send busy A when it is necessary to send a busy acknowledge (testing/diagnostics)
010 =
send a busy B when it is necessary to send a busy acknowledge (testing/diagnostics)
011 =
use single phase retry protocol
100 =
use protocol requested in packet, always send a busy ack (for all packets)
101 =
busy A all incoming packets
110 =
busy B all incoming packets are ‘1’
111 =
use single phase retry protocol, always send a busy ack
Transmitter Enable (TxENABLE): When this bit is set, the link layer transmitter will arbitrate and send packets.
Receiver Enable (RxENABLE): When this bit is set, the link layer receiver will receive and respond to bus packets.
Reset Transmitter (RSTTx): When set to one, this synchronously resets the transmitter within the link layer.
Reset Receiver (RSTRx): When set to one, this synchronously resets the receiver within the link layer.
Strict Isochronous (STRICTISOCH): Used to accept or reject isochronous packets sent outside of specified
isochronous cycles (between a Cycle Start and subaction gap). A ‘1’ rejects packets sent outside the specified
cycles, a “0” accepts isochronous packets sent outside the specified cycle.
Cycle Master (CYMASTER): When asserted and the PDI1394L21 is attached to the root PHY (ROOT bit = 1), and
the cycle_count field of the cycle timer register increments, the transmitter sends a cycle-start packet. Cycle Master
function will be disabled if a cycle timeout is detected (CYTMOUT bit 5 in LNKPHYINTACK). To restart the Cycle
Master function in such a case, first reset CYMASTER, then set it again.
Bit 30:
R/W
Bit 29..27:
R/W
Bit 26:
Bit 25:
Bit 21:
Bit 20:
Bit 12:
R/W
R/W
R/W
R/W
R/W
Bit 11:
R/W
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| PDI1394L41 | Content Protection AV Link Layer(內(nèi)容可保護(hù)的AV鏈接層控制器) |
| PDI1394P21 | 3-port Physical Layer Interface(三端口物理層接口) |
| PDI1394P22 | 3-port Physical Layer Interface(三端口物理層接口) |
| PDI1394P24 | 2-port 400 Mbps physical layer interface(2端口 400 Mbps物理層接口) |
| PDI40C1D00 | |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| PDI1394L21BE | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:1394 full duplex AV link layer controller |
| PDI1394L21BP | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:1394 full duplex AV link layer controller |
| PDI1394L40 | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:1394 enhanced AV link layer controller |
| PDI1394L40BE | 制造商:NXP Semiconductors 功能描述:1 CHANNEL(S), 400M BPS, SERIAL COMM CONTROLLER, PQFP144 |
| PDI1394L40BE,518 | 功能描述:視頻 IC 1394 A/V LINK LAYER RoHS:否 制造商:Fairchild Semiconductor 工作電源電壓:5 V 電源電流:80 mA 最大工作溫度:+ 85 C 封裝 / 箱體:TSSOP-28 封裝:Reel |
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