參數(shù)資料
型號(hào): PDI1394L21
廠(chǎng)商: NXP Semiconductors N.V.
英文描述: Full Duplex AV Link Layer Ccontroller(全雙工AV鏈接層控制器)
中文描述: 全雙工鏈路層Ccontroller影音(全雙工視聽(tīng)鏈接層控制器)
文件頁(yè)數(shù): 35/54頁(yè)
文件大?。?/td> 242K
代理商: PDI1394L21
Philips Semiconductors
Preliminary specification
PDI1394L21
1394 full duplex AV link layer controller
2000 Jun 06
35
13.2.4
The AV Transmitter Interrupt Control and Status register is the interrupt register for the AV transmitter.
Isochronous Transmitter Interrupt Acknowledge (ITXINTACK) – Base Address: 0x02C
Bits 2, 3, and 4 ”auto repair” themselves, i.e. AVLINK will detect the situation and attempt to recover on its own. The host controller still needs to
clear these interrupts to be alerted the next time.
29 28 272625 24 23 22 212019 18 1716 15 1413 12 11 10 9 8 7 6 5 4 3 2 1 0
D
I
I
D
I
T
T
SV00882
3130
I
I
I
Reset Value 0x00000000
Bits 9 .. 0 are interrupt acknowledge bits; and are defined as:
R/W
IT100LFT: Interrupt when transmitter queue reaches 100 quadlets from full. (924 of 1024 quadlets in queue)
R/W
IT256LFT: Interrupt when transmitter queue reaches 256 quadlets from full. (768 of 1024 quadlets in queue)
R/W
IT512LFT: Interrupt when transmitter queue reaches 50% of full. (512 of 1024 quadlets in queue)
R/W
TRMSYT: Interrupt on transmission of a SYT in CIP header quadlet 2
R/W
TRMBP: Interrupt on payload transmission/discard complete.
R/W
DBCERR: Acknowledge interrupt on Data Block Count (DBC) synchronization loss.
R/W
INPERR: Acknowledge interrupt on input error (input data discarded).
R/W
DISCARD: Interrupt on lost cycle (payload discarded).
R/W
ITXFULL: Interrupt on isochronous memory bank full. This is a fatal error, the recommended action is to reset and
re-initialize the transmitter.
R/W
ITXEMPTY: Interrupt on isochronous memory bank empty.
Other bits will always read ‘0’.
Bit 9:
Bit 8:
Bit 7:
Bit 6:
Bit 5:
Bit 4:
Bit 3:
Bit 2:
Bit 1:
Bit 0:
13.2.5
These are the enabled bits for the AV Transmitter Control.
Isochronous Transmitter Interrupt Enable (ITXINTE) – Base Address: 0x030
29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
8
7
6
5 4
3
2 1
0
E
E
E
E
E
E
E
31 30
SV00891
E
E
E
Reset Value 0x00000000
Bits 9..0 are interrupt enable bits for the Isochronous Transmitter Interrupt Acknowledge register (ITXINTACK).
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