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參數資料
| 型號： | PDI1394L21 |
| 廠商： | NXP Semiconductors N.V. |
| 英文描述： | Full Duplex AV Link Layer Ccontroller(全雙工AV鏈接層控制器) |
| 中文描述： | 全雙工鏈路層Ccontroller影音（全雙工視聽鏈接層控制器） |
| 文件頁數： | 11/54頁 |
| 文件大?。?/td> | 242K |
| 代理商： | PDI1394L21 |
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Philips Semiconductors
Preliminary specification
PDI1394L21
1394 full duplex AV link layer controller
2000 Jun 06
11
12.3.2
To write to an internal register the host interface must collect the 4 byte values into a 32 bit value and then write the result to the target register
in a single clock tick. This requires a register to hold the 32 bit value being compiled until it is ready to be written to the actual target register.
This temporary register inside the host interface is called the
write shadow register
. During all write cycles address lines HIF A0 and HIF A1
are used to select which of the 4 bytes of the
write shadow register
is to be written with the value on the CPU data bus. Only one byte can be
written in a single write access cycle.
Write accesses
UPDATE/COPY CONTROL
HIF A8
HIF A2..7
HIF A0..1
CPU
W
8
32
32
REGISTERS
TR
Q
Q
MUX
MUX
SV00804
NOTES:
1. It is not required to write all 4 bytes of a register: those bytes that are either reserved (undefined) or don’t care do not have to be written in
which case they will be assigned the value that was left in the corresponding byte of the
write shadow register
from a previous write
access. For example, to acknowledge an interrupt for the isochronous receiver (external address 0x04C), a single byte write to location
0x100+(0x4C)+3 = 0x14F is sufficient. The value 256 represents setting HIF A8=1. The host interface cannot directly access the FIFOs, but
instead reads from/writes into a transfer register (shown as TR in the Figures above). Data is moved between FIFO and TR by internal logic
as soon as possible without CPU intervention.
2. The update control line does not necessarily have to be connected to the CPU address line HIF A8. This input could also be controlled by
other means, for example a combinatorial circuit that activates the update control line whenever a write access is done for byte 3. This
makes the internal updating automatic for quadlet writing.
3. Writing the bytes of the read shadow register can be done in any order and as often as needed (new writes simply overwrite the old value).
12.3.3
The bytes in each quadlet are numbered 0..3 from left (most significant) to right (least significant) as shown in Figure 3. To access a register at
internal address N the CPU should use addresses E:
E = N
; to access the upper 8 bits of the register.
E = N + 1
; to access the upper middle 8 bits of the register.
E = N + 2
; to access the lower middle 8 bits of the register.
E = N + 3
; to access the lower 8 bits of the register.
Byte order
SV00656
29 28 272625 24 23 22 212019 18 1716 15 1413 12 11 10 9 8 7 6 5 4 3 2 1 0
BYTE 0
BYTE 1
BYTE 3
3130
BYTE 2
Figure 3. Byte order in quadlets as implemented in the host interface
12.3.4
Although entire incoming packets are stored in the receiver buffer memory they are not randomly accessible. These buffers act like FIFOs and
only the frontmost (oldest) data quadlet entry is accessible for reading. Therefore only one location (register address) is allocated to each of the
two receiver queues. Reading this location returns the head entry of the queue, and at the same time removes it from the queue, making the
next stored data quadlet accessible.
Accessing the packet queues
With the current host interface such a read is in fact a move operation of the data quadlet from the queue to the read shadow register. Once the
data is copied into the read shadow register it is no longer available in the queue itself so the CPU should always read all 4 bytes before
attempting any other read access (be careful with interrupt handlers for the PDI1394L21!).
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PDF描述 |
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| PDI1394P21 | 3-port Physical Layer Interface(三端口物理層接口) |
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相關代理商/技術參數 |
參數描述 |
|---|---|
| PDI1394L21BE | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:1394 full duplex AV link layer controller |
| PDI1394L21BP | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:1394 full duplex AV link layer controller |
| PDI1394L40 | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:1394 enhanced AV link layer controller |
| PDI1394L40BE | 制造商:NXP Semiconductors 功能描述:1 CHANNEL(S), 400M BPS, SERIAL COMM CONTROLLER, PQFP144 |
| PDI1394L40BE,518 | 功能描述:視頻 IC 1394 A/V LINK LAYER RoHS:否 制造商:Fairchild Semiconductor 工作電源電壓:5 V 電源電流:80 mA 最大工作溫度:+ 85 C 封裝 / 箱體:TSSOP-28 封裝:Reel |
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