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CHAPTER 10 WATCHDOG TIMER
User’s Manual U16228EJ2V0UD
244
10.4.3 Watchdog timer operation in STOP mode (when “Ring-OSC can be stopped by software” is selected
by mask option)
The watchdog timer stops counting during STOP instruction execution regardless of whether the X1 input clock or
Ring-OSC clock is being used.
(1) When the CPU clock and the watchdog timer operation clock are the X1 input clock (f
XP
) when the STOP
instruction is executed
When STOP instruction is executed, operation of the watchdog timer is stopped. After STOP mode is released,
counting stops for the oscillation stabilization time set by the oscillation stabilization time select register (OSTS)
and then counting is started again using the operation clock before the operation was stopped. At this time, the
counter is not cleared to 0 but holds its value.
Figure 10-4. Operation in STOP Mode (CPU Clock and WDT Operation Clock: X1 Input Clock)
Normal
operation
STOP
Oscillation stabilization time
Watchdog timer
Operating
Operation stopped
Operating
f
R
f
XP
CPU operation
Normal operation
Oscillation
stopped
Oscillation stabilization time
(set by OSTS register)
(2) When the CPU clock is the X1 input clock (f
XP
) and the watchdog timer operation clock is the Ring-OSC
clock (f
R
) when the STOP instruction is executed
When the STOP instruction is executed, operation of the watchdog timer is stopped. After STOP mode is
released, counting is started again using the operation clock before the operation was stopped. At this time, the
counter is not cleared to 0 but holds its value.
Figure 10-5. Operation in STOP Mode
(CPU Clock: X1 Input Clock, WDT Operation Clock: Ring-OSC Clock)
Normal
operation
STOP
Oscillation stabilization time
Watchdog timer
Operating
f
R
f
XP
CPU operation
Normal operation
Oscillation
stopped
Oscillation stabilization time
(set by OSTS register)
Operating Operation stopped