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CHAPTER 5 CLOCK GENERATOR
User’s Manual U16228EJ2V0UD
138
5.7 Time Required for CPU Clock Switchover
The CPU clock can be switched using bits 0 to 2 (PCC0 to PCC2) and bit 4 (CSS) of the processor clock control
register (PCC).
The actual switchover operation is not performed immediately after rewriting to the PCC; operation continues on
the pre-switchover clock for several instructions (see
Table 5-6
).
Whether the system is operating on the X1 input clock (or Ring-OSC clock) or the subsystem clock can be
ascertained using bit 5 (CLS) of the PCC register.
Table 5-6. Maximum Time Required for CPU Clock Switchover
Set Value Before
Switchover
Set Value After Switchover
CSS PCC2 PCC1 PCC0 CSS PCC2 PCC1 PCC0 CSS PCC2 PCC1 PCC0 CSS PCC2 PCC1 PCC0 CSS PCC2 PCC1 PCC0 CSS PCC2 PCC1 PCC0
CSS PCC2 PCC1 PCC0
0
0
0
0
0
0
0
1
0
0
1
0
0
0
1
1
0
1
0
0
1
×
×
×
0
0
0
16 clocks
16 clocks
16 clocks
16 clocks
f
XP
/f
XT
clocks
(306 clocks)
0
0
1
8 clocks
8 clocks
8 clocks
8 clocks
f
XP
/2f
XT
clocks
(153 clocks)
0
1
0
4 clocks
4 clocks
4 clocks
4 clocks
f
XP
/4f
XT
clocks
(77 clocks)
0
1
1
2 clocks
2 clocks
2 clocks
2 clocks
f
XP
/8f
XT
clocks
(39 clocks)
0
1
0
0
1 clock
1 clock
1 clock
1 clock
f
XP
/16f
XT
clocks
(20 clocks)
1
×
×
×
1 clock
1 clock
1 clock
1 clock
1 clock
Remarks 1.
The maximum time is the number of clocks of the pre-switchover CPU clock.
2.
Figures in parentheses apply to operation with f
XP
= 10 MHz and f
XT
= 32.768 kHz.
Caution Selection of the CPU clock cycle division factor (PCC0 to PCC2) and switchover from the X1
input clock to the subsystem clock (changing CSS from 0 to 1) should not be set
simultaneously.
Simultaneous setting is possible, however, for selection of the CPU clock cycle division factor
(PCC0 to PCC2) and switchover from the subsystem clock to the X1 input clock (changing CSS
from 1 to 0).