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CHAPTER 5 CLOCK GENERATOR
User’s Manual U16228EJ2V0UD
132
A status transition diagram of this product is shown in Figure 5-13, and the relationship between the operation
clocks in each operation status and between the oscillation control flag and oscillation status of each clock are shown
in Tables 5-3 and 5-4, respectively.
Figure 5-13. Status Transition Diagram (1/4)
(1) When “Ring-OSC can be stopped by software” is selected by mask option
(when subsystem clock is not used)
Status 4
CPU clock: f
XP
f
XP
: Oscillating
f
R
: Oscillation stopped
Status 3
CPU clock: f
XP
f
XP
: Oscillating
f
R
: Oscillating
Status 1
CPU clock: f
R
f
XP
: Oscillation stopped
f
R
: Oscillating
Status 2
CPU clock: f
R
f
XP
: Oscillating
f
R
: Oscillating
HALT
Note 4
Interrupt
Interrupt
Interrupt
Interrupt
Interrupt
Interrupt
Reset release
Interrupt
Interrupt
HALT
instruction
STOP
instruction
STOP
instruction
STOP
instruction
STOP
instruction
RSTOP = 0
RSTOP = 1
Note 1
MCM0 = 0
MCM0 = 1
Note 2
MSTOP = 1
Note 3
MSTOP = 0
HALT
instruction
HALT instruction
HALT
instruction
STOP
Note 4
Reset
Note 5
Notes 1.
When shifting from status 3 to status 4, make sure that bit 1 (MCS) of the main clock mode register
(MCM) is 1.
2.
Before shifting from status 2 to status 3 after reset and STOP are released, check the X1 input clock
oscillation stabilization time status using the oscillation stabilization time counter status register
(OSTC).
3.
When shifting from status 2 to status 1, make sure that MCS is 0.
4.
When “Ring-OSC can be stopped by software” is selected by a mask option, the watchdog timer
stops operating in the HALT and STOP modes, regardless of the source clock of the watchdog timer.
However, oscillation of Ring-OSC does not stop even in the HALT and STOP modes if RSTOP = 0.
5.
All reset sources (RESET input, POC, LVI, clock monitor, and WDT)