參數(shù)資料
型號: PCA9698
廠商: NXP Semiconductors N.V.
英文描述: 40-bit Fm+ I2C-bus advanced I/O port with RESET, OE and INT
中文描述: 40位調(diào)頻I2C總線先進(jìn)的I / O復(fù)位,光電和INT端口
文件頁數(shù): 23/47頁
文件大?。?/td> 214K
代理商: PCA9698
PCA9698_2
Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Product data sheet
Rev. 02 — 19 July 2006
23 of 47
Philips Semiconductors
PCA9698
40-bit Fm+ I
2
C-bus advanced I/O port with RESET, OE and INT
8.
Characteristics of the I
2
C-bus
The I
2
C-bus is for 2-way, 2-line communication between different ICs or modules. The two
lines are a serial data line (SDA) and a serial clock line (SCL). Both lines must be
connected to a positive supply via a pull-up resistor when connected to the output stages
of a device. Data transfer may be initiated only when the bus is not busy.
8.1 Bit transfer
One data bit is transferred during each clock pulse. The data on the SDA line must remain
stable during the HIGH period of the clock pulse as changes in the data line at this time
will be interpreted as control signals (see
Figure 11
).
8.1.1
START and STOP conditions
Both data and clock lines remain HIGH when the bus is not busy. A HIGH-to-LOW
transition of the data line while the clock is HIGH is defined as the START condition (S). A
LOW-to-HIGH transition of the data line while the clock is HIGH is defined as the STOP
condition (P) (see
Figure 12
.)
Fig 11. Bit transfer
mba607
data line
stable;
data valid
change
of data
allowed
SDA
SCL
Fig 12. Definition of START and STOP conditions
mba608
SDA
SCL
P
STOP condition
SDA
SCL
S
START condition
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