參數(shù)資料
型號： PCA9698
廠商： NXP Semiconductors N.V.
英文描述： 40-bit Fm+ I2C-bus advanced I/O port with RESET, OE and INT
中文描述： 40位調(diào)頻I2C總線先進的I / O復位，光電和INT端口
文件頁數(shù)： 13/47頁
文件大小： 214K
代理商： PCA9698
PCA9698_2
Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Product data sheet
Rev. 02 — 19 July 2006
13 of 47
Philips Semiconductors
PCA9698
40-bit Fm+ I
2
C-bus advanced I/O port with RESET, OE and INT
7.4.5
MSK0 to MSK4 - Mask interrupt registers
These registers mask the interrupt due to a change in the I/O pins configured as inputs. ‘x’
refers to the bank number (0 to 4); ‘y’ refers to the bit number (0 to 7).
Mx[y] = 0: A level change at the I/O will generate an interrupt if IOx_y defined as input
(Cx[y] in IOC register = 1).
Mx[y] = 1: A level change in the input port will not generate an interrupt if IOx_y defined
as input (Cx[y] in IOC register = 1).
7.4.6
OUTCONF - output structure configuration register
This register controls the configuration of the output ports as open-drain or totem-pole.
The 4 least significant bits control the output architecture for bank 0, 2 bits at a time.
OUT001 controls the output structure for IO0_0 and IO0_1
OUT023 controls the output structure for IO0_2 and IO0_3
OUT045 controls the output structure for IO0_4 and IO0_5
OUT067 controls the output structure for IO0_6 and IO0_7
The 4 most significant bits control the output architectures for bank 1 to bank 4, each bit
controlling one bank.
OUT1 controls the output structure for bank 1 (IO1_0 to IO1_7)
OUT2 controls the output structure for bank 2 (IO2_0 to IO2_7)
OUT3 controls the output structure for bank 3 (IO3_0 to IO3_7)
OUT4 controls the output structure for bank 4 (IO4_0 to IO4_7)
OUTx = 0: The I/Os are configured with an open-drain structure.
OUTx = 1: The I/Os are configured with a totem-pole structure.
Table 8.
Legend: * default value.
Address
20h
21h
22h
23h
24h
MSK0 to MSK4 - Mask interrupt registers (address 20h to 24h) bit description
Register
MSK0
MSK1
MSK2
MSK3
MSK4
Bit
7 to 0
7 to 0
7 to 0
7 to 0
7 to 0
Symbol
M0[7:0]
M1[7:0]
M2[7:0]
M3[7:0]
M4[7:0]
Access
R/W
R/W
R/W
R/W
R/W
Value
1111 1111*
1111 1111*
1111 1111*
1111 1111*
1111 1111*
Description
Mask Interrupt register bank 0
Mask Interrupt register bank 1
Mask Interrupt register bank 2
Mask Interrupt register bank 3
Mask Interrupt register bank 4
Table 9.
Bit
Symbol
Default
OUTCONF - output structure configuration register (address 28h) description
7
6
5
4
OUT4
OUT3
OUT2
OUT1
1
1
1
1
3
2
1
0
OUT067
1
OUT045
1
OUT023
1
OUT001
1
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