參數(shù)資料
型號(hào)： PCA9698
廠商： NXP Semiconductors N.V.
英文描述： 40-bit Fm+ I2C-bus advanced I/O port with RESET, OE and INT
中文描述： 40位調(diào)頻I2C總線先進(jìn)的I / O復(fù)位，光電和INT端口
文件頁(yè)數(shù)： 11/47頁(yè)
文件大?。?/td> 214K
代理商： PCA9698
PCA9698_2
Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Product data sheet
Rev. 02 — 19 July 2006
11 of 47
Philips Semiconductors
PCA9698
40-bit Fm+ I
2
C-bus advanced I/O port with RESET, OE and INT
7.4.1
IP0 to IP4 - Input Port registers
These registers are read-only. They reflect the incoming logic levels of the port pins
regardless of whether the pin is defined as an input or an output by the I/O Configuration
register. If the corresponding Px[y] bit in the PI registers is set to 0, or the inverted
incoming logic levels if the corresponding Px[y] bit in the PI register is set to 1. Writes to
these registers have no effect.
The Polarity Inversion register can invert the logic states of the port pins. The polarity of
the corresponding bit is inverted when Px[y] bit in the PI register is set to 1. The polarity of
the corresponding bit is not inverted when Px[y] bits in the PI register is set to 0.
7.4.2
OP0 to OP4 - Output Port registers
These registers reflect the outgoing logic levels of the pins defined as outputs by the
I/O Configuration register. Bit values in these registers have no effect on pins defined as
inputs. In turn, reads from these registers reflect the values that are in the flip-flops
controlling the output selection,
not
the actual pin values.
Ox[y] = 0: IOx_y = 0 if IOx_y defined as output (Cx[y] in IOC register = 0).
Ox[y] = 1: IOx_y = 1 if IOx_y defined as output (Cx[y] in IOC register = 0).
Where ‘x’ refers to the bank number (0 to 4); ‘y’ refers to the bit number (0 to 7).
Table 4.
Legend: * default value ‘X’ determined by the externally applied logic level.
Address
Register
Bit
00h
IP0
7 to 0
01h
IP1
7 to 0
02h
IP2
7 to 0
03h
IP3
7 to 0
04h
IP4
7 to 0
IP0 to IP4 - Input Port registers (address 00h to 04h) bit description
Symbol
I0[7:0]
I1[7:0]
I2[7:0]
I3[7:0]
I4[7:0]
Access
R
R
R
R
R
Value
XXXX XXXX*
XXXX XXXX*
XXXX XXXX*
XXXX XXXX*
XXXX XXXX*
Description
Input Port register bank 0
Input Port register bank 1
Input Port register bank 2
Input Port register bank 3
Input Port register bank 4
Table 5.
Legend: * default value.
Address
08h
09h
0Ah
0Bh
0Ch
OP0 to OP4 - Output Port registers (address 08h to 0Ch) bit description
Register
OP0
OP1
OP2
OP3
OP4
Bit
7 to 0
7 to 0
7 to 0
7 to 0
7 to 0
Symbol
O0[7:0]
O1[7:0]
O2[7:0]
O3[7:0]
O4[7:0]
Access
R/W
R/W
R/W
R/W
R/W
Value
0000 0000*
0000 0000*
0000 0000*
0000 0000*
0000 0000*
Description
Output Port register bank 0
Output Port register bank 1
Output Port register bank 2
Output Port register bank 3
Output Port register bank 4
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