參數(shù)資料
型號(hào)： PC56F8006VWL
廠商： Freescale Semiconductor
文件頁數(shù)： 73/106頁
文件大小： 0K
描述： DSP 16BIT 28-SOIC
標(biāo)準(zhǔn)包裝： 26
系列： 56F8xxx
核心處理器： 56800
芯體尺寸： 16-位
速度： 32MHz
連通性： I²C，LIN，SCI，SPI
外圍設(shè)備： LVD，POR，PWM，WDT
輸入/輸出數(shù)： 23
程序存儲(chǔ)器容量： 16KB（8K x 16）
程序存儲(chǔ)器類型： 閃存
RAM 容量： 1K x 16
電壓 - 電源 (Vcc/Vdd)： 1.8 V ~ 3.6 V
數(shù)據(jù)轉(zhuǎn)換器： A/D 15x12b
振蕩器型： 內(nèi)部
工作溫度： -40°C ~ 105°C
封裝/外殼： 28-SOIC（0.295"，7.50mm 寬）
包裝： 管件
Specifications
MC56F8006/MC56F8002 Digital Signal Controller, Rev. 4
Freescale Semiconductor
69
Power consumption is given by the following equation:
Eqn. 1
A, the internal [static] component, is comprised of the DC bias currents for the oscillator, leakage currents, PLL, and voltage
references. These sources operate independently of processor state or operating frequency.
B, the internal [state-dependent] component, reflects the supply current required by certain on-chip resources only when those
resources are in use. These include RAM, flash memory, and the ADCs.
C, the internal [dynamic] component, is classic C*V2*F CMOS power dissipation corresponding to the 56800E core and
standard cell logic.
D, the external [dynamic] component, reflects power dissipated on-chip as a result of capacitive loading on the external pins of
the chip. This is also commonly described as C*V2*F, although simulations on two of the I/O cell types used on the 56800E
reveal that the power-versus-load curve does have a non-zero Y-intercept.
Power due to capacitive loading on output pins is (first order) a function of the capacitive load and frequency at which the
outputs change. Table 39 provides coefficients for calculating power dissipated in the I/O cells as a function of capacitive load.
In these cases:
TotalPower =
((Intercept + Slope*Cload)*frequency/10 MHz)
Eqn. 2
where:
Summation is performed over all output pins with capacitive loads
Total power is expressed in mW
Cload is expressed in pF
Because of the low duty cycle on most device pins, power dissipation due to capacitive loads was found to be fairly low when
averaged over a period of time.
E, the external [static component], reflects the effects of placing resistive loads on the outputs of the device. Sum the total of
all V2/R or IV to arrive at the resistive load contribution to power. Assume V = 0.5 for the purposes of these rough calculations.
For instance, if there is a total of eight PWM outputs driving 10 mA into LEDs, then P = 8*0.5*0.01 = 40 mW.
In previous discussions, power consumption due to parasitics associated with pure input pins is ignored, as it is assumed to be
negligible.
Total power =
A:
internal [static component]
+B: internal [state-dependent component]
+C:
internal [dynamic component]
+D:
external [dynamic component]
+E:
external [static component]
Table 39. I/O Loading Coefficients at 10 MHz
Intercept
Slope
8 mA drive
1.3
0.11 mW/pF
4 mA drive
1.15 mW
0.11 mW/pF
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