參數(shù)資料
型號： PC56F8006VWL
廠商： Freescale Semiconductor
文件頁數(shù)： 38/106頁
文件大?。?/td> 0K
描述： DSP 16BIT 28-SOIC
標準包裝： 26
系列： 56F8xxx
核心處理器： 56800
芯體尺寸： 16-位
速度： 32MHz
連通性： I²C，LIN，SCI，SPI
外圍設備： LVD，POR，PWM，WDT
輸入/輸出數(shù)： 23
程序存儲器容量： 16KB（8K x 16）
程序存儲器類型： 閃存
RAM 容量： 1K x 16
電壓 - 電源 (Vcc/Vdd)： 1.8 V ~ 3.6 V
數(shù)據(jù)轉(zhuǎn)換器： A/D 15x12b
振蕩器型： 內(nèi)部
工作溫度： -40°C ~ 105°C
封裝/外殼： 28-SOIC（0.295"，7.50mm 寬）
包裝： 管件
General System Control Information
MC56F8006/MC56F8002 Digital Signal Controller, Rev. 4
Freescale Semiconductor
37
Figure 13. Connecting an External Clock Signal Using XTAL
6.4.4
Alternate External Clock Input
The recommended method of connecting an external clock is illustrated in Figure 14. The external clock source is connected
to GPIOB6/RXD/SDA/ANA13 and CMP0_P2/CLKIN while EXT_SEL bit in OSCTL register is set and corresponding bits in
GPIOB_PER register GPIO module and GPSB1 register in the system integration module (SIM) are set to the correct values.
The external clock input must be generated using a relatively low impedance driver with maximum frequency not greater than
64 MHz.
Figure 14. Connecting an External Clock Signal Using GPIO
6.5
Interrupt Controller
The 56F8006/56F8002 interrupt controller (INTC) module arbitrates the various interrupt requests (IRQs). The INTC signals
to the 56800E core when an interrupt of sufficient priority exists and what address to jump to to service this interrupt.
The interrupt controller contains registers that allow up to three interrupt sources to be set to priority level 1 and other up to
three interrupt sources to be set to priority level 2. By default, all peripheral interrupt sources are set to priority level 0. Next,
all of the interrupt requests of a given level are priority encoded to determine the lowest numeric value of the active interrupt
requests for that level. Within a given priority level, the lowest vector number is the highest priority and the highest vector
number is the lowest.
The highest vector number, a user assignable vector USER6 (vector 50), can be defined as a fast interrupt if the instruction
located in this vector location is not a JSR or BSR instruction. Please see section 9.3.3.3 of DSP56800E 16-Bit Core Reference
Manual for detail.
6.6
System Integration Module (SIM)
The SIM module is a system catchall for the glue logic that ties together the system-on-chip. It controls distribution of resets
and clocks and provides a number of control features including the pin muxing control; inter-module connection control (for
example connecting comparator output to PWM fault input); individual peripheral enable/disable; PWM, timer, and SCI clock
rate control; enabling peripheral operation in stop mode; port configuration overwrite protection. For further information, see
the MC56F8006 Peripheral Reference Manual.
The SIM is responsible for the following functions:
Chip reset sequencing
Core and peripheral clock control and distribution
Stop/wait mode control
System status control
EXTAL
XTAL
56F8006/56F8002
External Clock
(<50 MHz)
GND or GPIO
CLK_MOD = 1
56F8002/56F8006
GPIOB6/RXD/SDA/ANA13 and CMP0_P2/CLKIN
External Clock (
64 MHz)
EXT_SEL = 1;
GPIO_B_PER[6] = 0;
GPS_B6 = 11
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