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Chapter 2 Port Integration Module (S12XEPIMV1)
MC9S12XE-Family Reference Manual Rev. 1.07
Freescale Semiconductor
169
2.3.102 Port F Input Register (PTIF)
2.3.103 Port F Data Direction Register (DDRF)
1
PTF
Port F general purpose input/output data
—Data Register
Port F pin 3 is associated with the TXD signal of the SCI4 module.
When not used with the alternative function, this pin can be used as general purpose I/O.
If the associated data direction bit of this pin is set to 1, a read returns the value of the port register, otherwise the
buffered pin input state is read.
0
PTF
Port F general purpose input/output data
—Data Register
Port F pin 2 is associated with the RXD signal of the SCI4 module.
When not used with the alternative function, this pin can be used as general purpose I/O.
If the associated data direction bit of this pin is set to 1, a read returns the value of the port register, otherwise the
buffered pin input state is read.
Address 0x0379
Access: User read
1
1
Read: Anytime.
Write:Never, writes to this register have no effect.
7
6
5
4
3
2
1
0
R
PTIF7
PTIF6
PTIF5
PTIF4
PTIF3
PTIF2
PTIF1
PTIF0
W
Reset
u
u
u
u
u
u
u
u
= Unimplemented or Reserved
u = Unaffected by reset
Figure 2-100. Port F Input Register (PTIF)
Table 2-96. PTIF Register Field Descriptions
Field
Description
7-0
PTIF
Port F input data
—
This register always reads back the buffered state of the associated pins. This can also be used to detect overload
or short circuit conditions on output pins.
Address 0x037A
Access: User read/write
1
1
Read: Anytime.
Write: Anytime.
7
6
5
4
3
2
1
0
R
DDRF7
DDRF6
DDRF5
DDRF4
DDRF3
DDRF2
DDRF1
DDRF0
W
Reset
0
0
0
0
0
0
0
0
Figure 2-101. Port F Data Direction Register (DDRF)
Table 2-95. PTF Register Field Descriptions (continued)
Field
Description