
Chapter 14 Enhanced Capture Timer (ECT16B8CV3)
MC9S12XE-Family Reference Manual Rev. 1.07
Freescale Semiconductor
567
14.4.2.20 16-Bit Modulus Down-Counter FLAG Register (MCFLG)
Read: Anytime
Write only used in the flag clearing mechanism for bit 7. Writing a one to bit 7 clears the flag. Writing a
zero will not affect the current status of the bit.
NOTE
When TFFCA = 1, the flag cannot be cleared via the normal flag clearing
mechanism (writing a one to the flag). Reference
Section 14.4.2.6, “Timer
System Control Register 1 (TSCR1)”
.
All bits reset to zero.
Table 14-22. Modulus Counter Prescaler Select
MCPR1
MCPR0
Prescaler Division
0
0
1
0
1
4
1
0
8
1
1
16
Module Base + 0x0027
7
6
0
5
0
4
0
3
2
1
0
R
W
MCZF
POLF3
POLF2
POLF1
POLF0
Reset
0
0
0
0
0
0
0
0
= Unimplemented or Reserved
Figure 14-42. 16-Bit Modulus Down-Counter FLAG Register (MCFLG)
Table 14-23. MCFLG Field Descriptions
Field
Description
7
MCZF
Modulus Counter Underflow Flag
— The flag is set when the modulus down-counter reaches 0x0000.
The flag indicates when interrupt conditions have occurred. The flag can be cleared via the normal flag clearing
mechanism (writing a one to the flag) or via the fast flag clearing mechanism (Reference TFFCA bit in
Section 14.4.2.6, “Timer System Control Register 1 (TSCR1)”
).
3:0
POLF[3:0]
First Input Capture Polarity Status
— These are read only bits. Writes to these bits have no effect.
Each status bit gives the polarity of the first edge which has caused an input capture to occur after capture latch
has been read.
Each POLFx corresponds to a timer PORTx input.
0 The first input capture has been caused by a falling edge.
1 The first input capture has been caused by a rising edge.