參數(shù)資料
型號： P89LPC9107FN,112
廠商： NXP Semiconductors
文件頁數(shù)： 6/39頁
文件大?。?/td> 0K
描述： IC 80C51 MCU FLASH 1K 14-DIP
標(biāo)準(zhǔn)包裝： 28
系列： LPC900
核心處理器： 8051
芯體尺寸： 8-位
速度： 18MHz
連通性： UART/USART
外圍設(shè)備： 欠壓檢測/復(fù)位，LED，POR，PWM，WDT
輸入/輸出數(shù)： 12
程序存儲器容量： 1KB（1K x 8）
程序存儲器類型： 閃存
RAM 容量： 128 x 8
電壓 - 電源 (Vcc/Vdd)： 2.4 V ~ 3.6 V
數(shù)據(jù)轉(zhuǎn)換器： A/D 4x10b
振蕩器型： 內(nèi)部
工作溫度： -40°C ~ 85°C
封裝/外殼： 14-DIP（0.300"，7.62mm）
包裝： 管件
配用： DB-TSSOP-LPC9107-ND - BOARD FOR LPC9107 TSSOP
622-1006-ND - SOCKET ADAPTER BOARD
622-1003-ND - KIT FOR LCD DEMO
568-1759-ND - EMULATOR DEBUGGER/PROGRMMR LPC9X
其它名稱： 935282288112
P89LPC9107FN
P89LPC9107FN-ND
P89LPC9102_9103_9107_3
NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 03 — 10 July 2007
14 of 61
NXP Semiconductors
P89LPC9102/9103/9107
8-bit microcontrollers with two-clock accelerated 80C51 core
P1.0 to P1.2,
P1.5
I/O
Port 1: Port 1 is an I/O port with a user-congurable output type. During reset Port 1
latches are congured in the input-only mode with the internal pull-up disabled. The
operation of the congurable Port 1 pins as inputs and outputs depends upon the port
conguration selected. Each of the congurable port pins are programmed
characteristics” for details. P1.5 is input-only.
All pins have Schmitt triggered inputs.
Port 1 also provides various special functions as described below:
P1.0/TXD
6
I/O
P1.0 — Port 1 bit 0.
O
TXD — Serial port transmitter data.
P1.1/RXD
9
I/O
P1.1 — Port 1 bit 1.
I
RXD — Serial port receiver data.
P1.2/T0
7
I/O
P1.2 — Port 1 bit 2.
I/O
T0 — Timer/counter 0 external count input or overow/PWM output.
P1.5/RST
3
I
P1.5 — Port 1 bit 5 (input-only).
I
RST — External Reset input during Power-on or if selected via UCFG1. When
functioning as a reset input a LOW on this pin resets the microcontroller, causing I/O
ports and peripherals to take on their default states, and the processor begins
execution at address 0. When using an oscillator frequency above 12 MHz, the
reset input function of P1.5 must be enabled. An external circuit is required to
hold the device in reset at power-up until VDD has reached its specied level.
When system power is removed VDD will fall below the minimum specied
operating voltage. When using an oscillator frequency above 12 MHz, in some
applications, an external brownout detect circuit may be required to hold the
device in reset when VDD falls below the minimum specied operating voltage.
VSS
4I
Ground: 0 V reference.
VDD
10
I
Power supply: This is the power supply voltage for normal operation as well as Idle
mode and Power-down mode.
Table 6.
P89LPC9107 pin description …continued
Symbol
Pin
Type
Description
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