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參數(shù)資料
| 型號： | P89LPC9107FN,112 |
| 廠商： | NXP Semiconductors |
| 文件頁數(shù)： | 22/39頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC 80C51 MCU FLASH 1K 14-DIP |
| 標準包裝： | 28 |
| 系列： | LPC900 |
| 核心處理器： | 8051 |
| 芯體尺寸： | 8-位 |
| 速度： | 18MHz |
| 連通性： | UART/USART |
| 外圍設(shè)備： | 欠壓檢測/復(fù)位，LED，POR，PWM，WDT |
| 輸入/輸出數(shù)： | 12 |
| 程序存儲器容量： | 1KB（1K x 8） |
| 程序存儲器類型： | 閃存 |
| RAM 容量： | 128 x 8 |
| 電壓 - 電源 (Vcc/Vdd)： | 2.4 V ~ 3.6 V |
| 數(shù)據(jù)轉(zhuǎn)換器： | A/D 4x10b |
| 振蕩器型： | 內(nèi)部 |
| 工作溫度： | -40°C ~ 85°C |
| 封裝/外殼： | 14-DIP（0.300"，7.62mm） |
| 包裝： | 管件 |
| 配用： | DB-TSSOP-LPC9107-ND - BOARD FOR LPC9107 TSSOP 622-1006-ND - SOCKET ADAPTER BOARD 622-1003-ND - KIT FOR LCD DEMO 568-1759-ND - EMULATOR DEBUGGER/PROGRMMR LPC9X |
| 其它名稱： | 935282288112 P89LPC9107FN P89LPC9107FN-ND |
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P89LPC9102_9103_9107_3
NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 03 — 10 July 2007
29 of 61
NXP Semiconductors
P89LPC9102/9103/9107
8-bit microcontrollers with two-clock accelerated 80C51 core
frequency above 12 MHz, in some applications, an external brownout detect circuit
may be required to hold the device in reset when VDD falls below the minimum
specied operating voltage.
8.7 CCLK wake-up delay
The P89LPC9102/9103/9107 has an internal wake-up timer that delays the clock until it
stabilizes depending to the clock source used.
8.8 CCLK modication: DIVM register
The OSCCLK frequency can be divided down up to 510 times by conguring a dividing
register, DIVM, to generate CCLK. This feature makes it possible to temporarily run the
CPU at a lower rate, reducing power consumption. By dividing the clock, the CPU can
retain the ability to respond to events that would not exit Idle mode by executing its normal
program at a lower rate. This can also allow bypassing the oscillator start-up time in cases
where Power-down mode would otherwise be used. The value of DIVM may be changed
by the program at any time without interrupting code execution.
8.9 Low power select
If CCLK is 8 MHz or slower, the CLKLP SFR bit (AUXR1.7) can be set to logic 1 to lower
the power consumption further. On any reset, CLKLP is logic 0.
8.10 Memory organization
The various P89LPC9102/9103/9107 memory spaces are as follows:
DATA
128 bytes of internal data memory space (00H:7FH) accessed via direct or indirect
addressing, using instruction other than MOVX and MOVC. All or part of the stack
may be in this area.
SFR
Special Function Registers. Selected CPU registers and peripheral control and status
registers, accessible only via direct addressing.
CODE
1 kB of Code memory space, accessed as part of program execution and via the
MOVC instruction.
8.11 Interrupts
The P89LPC9102 supports nine interrupt sources: timers 0 and 1, brownout detect,
watchdog timer/RTC, keyboard, comparator 1, and the A/D converter.
The P89LPC9103/9107 support nine interrupt sources: timers 0 and 1, serial port Tx,
serial port Rx, combined serial port Rx/Tx, brownout detect, watchdog timer/RTC,
keyboard, comparator, and the A/D converter.
Each interrupt source can be individually enabled or disabled by setting or clearing a bit in
the interrupt enable registers IEN0 or IEN1. The IEN0 register also contains a global
disable bit, EA, which disables all interrupts.
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