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參數(shù)資料
| 型號(hào)： | P89LPC9107FN,112 |
| 廠商： | NXP Semiconductors |
| 文件頁(yè)數(shù)： | 20/39頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC 80C51 MCU FLASH 1K 14-DIP |
| 標(biāo)準(zhǔn)包裝： | 28 |
| 系列： | LPC900 |
| 核心處理器： | 8051 |
| 芯體尺寸： | 8-位 |
| 速度： | 18MHz |
| 連通性： | UART/USART |
| 外圍設(shè)備： | 欠壓檢測(cè)/復(fù)位，LED，POR，PWM，WDT |
| 輸入/輸出數(shù)： | 12 |
| 程序存儲(chǔ)器容量： | 1KB（1K x 8） |
| 程序存儲(chǔ)器類型： | 閃存 |
| RAM 容量： | 128 x 8 |
| 電壓 - 電源 (Vcc/Vdd)： | 2.4 V ~ 3.6 V |
| 數(shù)據(jù)轉(zhuǎn)換器： | A/D 4x10b |
| 振蕩器型： | 內(nèi)部 |
| 工作溫度： | -40°C ~ 85°C |
| 封裝/外殼： | 14-DIP（0.300"，7.62mm） |
| 包裝： | 管件 |
| 配用： | DB-TSSOP-LPC9107-ND - BOARD FOR LPC9107 TSSOP 622-1006-ND - SOCKET ADAPTER BOARD 622-1003-ND - KIT FOR LCD DEMO 568-1759-ND - EMULATOR DEBUGGER/PROGRMMR LPC9X |
| 其它名稱： | 935282288112 P89LPC9107FN P89LPC9107FN-ND |
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P89LPC9102_9103_9107_3
NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 03 — 10 July 2007
27 of 61
NXP Semiconductors
P89LPC9102/9103/9107
8-bit microcontrollers with two-clock accelerated 80C51 core
8.2 Enhanced CPU
The P89LPC9102/9103/9107 uses an enhanced 80C51 CPU which runs at six times the
speed of standard 80C51 devices. A machine cycle consists of two CPU clock cycles, and
most instructions execute in one or two machine cycles.
8.3 Clocks
8.3.1 Clock denitions
The P89LPC9102/9103/9107 device has internal clocks as dened below:
OSCCLK — Input to the DIVM clock divider. OSCCLK is selected from one of the clock
sources (see Figure 11 “Block diagram of P89LPC9102 oscillator control”) and can also
be optionally divided to a slower frequency (see Section 8.8 “CCLK modication: DIVM
Note: fosc is dened as the OSCCLK frequency.
CCLK — CPU clock; output of the clock divider. There are two CCLK cycles per machine
cycle, and most instructions are executed in one to two machine cycles (two or four CCLK
cycles).
RCCLK — The internal 7.373 MHz RC oscillator output. The clock doubler option, when
enabled, provides an output frequency of 14.746 MHz.
PCLK — Clock for the various peripheral devices and is CCLK
2.
8.3.2 CPU clock (CCLK)
The P89LPC9102/9103/9107 provides user-selectable oscillator options in generating the
CPU clock. This allows optimization for a range of needs from high precision to lowest
possible cost. These options are congured when the ash memory is programmed and
include an on-chip watchdog oscillator, an on-chip RC oscillator, and an external clock
input.
8.4 On-chip RC oscillator option
The P89LPC9102/9103/9107 has a 6-bit TRIM register that can be used to tune the
frequency of the RC oscillator. During reset, the TRIM value is initialized to a factory
pre-programmed value to adjust the oscillator frequency to 7.373 MHz
± 1 % at room
temperature. End-user applications can write to the Trim register to adjust the on-chip RC
oscillator to other frequencies. When the clock doubler option is enabled (UCFG1.3 = 1)
the output frequency is 14.746 MHz. If CCLK is 8 MHz or slower, the CLKLP SFR bit
(AUXR1.7) can be set to logic 1 to reduce power consumption. On reset, CLKLP is logic 0
allowing highest performance access. This bit can then be set in software if CCLK is
running at 8 MHz or slower.
The RCCLK bit (TRIM.7) can be used to switch between the clock source selected by
UCFG1 and the internal RC oscillator. This allows a low frequency source such as the
WDT or low speed external source to clock the device in order to save power and then
switch to the higher speed internal RC oscillator to perform processing.
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