參數(shù)資料
型號: P89LPC9107FN,112
廠商: NXP Semiconductors
文件頁數(shù): 33/39頁
文件大?。?/td> 0K
描述: IC 80C51 MCU FLASH 1K 14-DIP
標(biāo)準(zhǔn)包裝: 28
系列: LPC900
核心處理器: 8051
芯體尺寸: 8-位
速度: 18MHz
連通性: UART/USART
外圍設(shè)備: 欠壓檢測/復(fù)位,LED,POR,PWM,WDT
輸入/輸出數(shù): 12
程序存儲器容量: 1KB(1K x 8)
程序存儲器類型: 閃存
RAM 容量: 128 x 8
電壓 - 電源 (Vcc/Vdd): 2.4 V ~ 3.6 V
數(shù)據(jù)轉(zhuǎn)換器: A/D 4x10b
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 85°C
封裝/外殼: 14-DIP(0.300",7.62mm)
包裝: 管件
配用: DB-TSSOP-LPC9107-ND - BOARD FOR LPC9107 TSSOP
622-1006-ND - SOCKET ADAPTER BOARD
622-1003-ND - KIT FOR LCD DEMO
568-1759-ND - EMULATOR DEBUGGER/PROGRMMR LPC9X
其它名稱: 935282288112
P89LPC9107FN
P89LPC9107FN-ND
P89LPC9102_9103_9107_3
NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 03 — 10 July 2007
39 of 61
NXP Semiconductors
P89LPC9102/9103/9107
8-bit microcontrollers with two-clock accelerated 80C51 core
8.21 Comparator interrupt
The comparator has an interrupt ag contained in its conguration register. This ag is set
whenever the comparator output changes state. The ag may be polled by software or
may be used to generate an interrupt.
8.22 Comparator and power reduction modes
The comparator may remain enabled when Power-down mode or Idle mode is activated,
but the comparator is disabled automatically in Total Power-down mode.
If the comparator interrupt is enabled (except in Total Power-down mode), a change of the
comparator output state will generate an interrupt and wake-up the processor. If the
comparator output to a pin is enabled, the pin should be congured in the push-pull mode
in order to obtain fast switching times while in Power-down mode. The reason is that with
the oscillator stopped, the temporary strong pull-up that normally occurs during switching
on a quasi-bidirectional port pin does not take place.
The comparator consumes power in Power-down mode and Idle mode, as well as in the
normal operating mode. This fact should be taken into account when system power
consumption is an issue. To minimize power consumption, the user can disable the
comparator via PCONA.5 or put the device in Total Power-down mode.
8.23 Keypad interrupt (KBI)
The Keypad Interrupt function is intended primarily to allow a single interrupt to be
generated when Port 0 is equal to or not equal to a certain pattern. This function can be
used for bus address recognition or keypad recognition. The user can congure the port
via SFRs for different tasks.
The Keypad Interrupt Mask Register (KBMASK) is used to dene which input pins
connected to Port 0 can trigger the interrupt. The Keypad Pattern Register (KBPATN) is
used to dene a pattern that is compared to the value of Port 0. The Keypad Interrupt Flag
(KBIF) in the Keypad Interrupt Control Register (KBCON) is set when the condition is
matched while the Keypad Interrupt function is active. An interrupt will be generated if
enabled. The PATN_SEL bit in the Keypad Interrupt Control Register (KBCON) is used to
dene equal or not-equal for the comparison.
In order to use the Keypad Interrupt as an original KBI function like in 87LPC76x series,
the user needs to set KBPATN = 0FFH and PATN_SEL = 1 (not equal), then any key
connected to Port 0 which is enabled by the KBMASK register will cause the hardware to
set KBIF and generate an interrupt if it has been enabled. The interrupt may be used to
wake-up the CPU from Idle mode or Power-down mode. This feature is particularly useful
in handheld, battery powered systems that need to carefully manage power consumption
yet also need to be convenient to use.
In order to set the ag and cause an interrupt, the pattern on Port 0 must be held longer
than six CCLKs.
8.24 Watchdog timer
The watchdog timer causes a system reset when it underows as a result of a failure to
feed the timer prior to the timer reaching its terminal count. It consists of a programmable
12-bit prescaler, and an 8-bit down counter. The down counter is decremented by a tap
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