參數(shù)資料
型號: ORT4622
英文描述: Field-Programmable System Chip (FPSC) Four-Channel x 622 Mbits/s Backplane Transceiver
中文描述: 現(xiàn)場可編程系統(tǒng)芯片(促進(jìn)文化基金)四通道x 622 Mbits /秒背板收發(fā)器
文件頁數(shù): 53/90頁
文件大小: 1915K
代理商: ORT4622
Lucent Technologies Inc.
Lucent Technologies Inc.
53
Preliminary Data Sheet
March 2000
ORCA ORT4622 FPSC
Four-Channel x 622 Mbits/s Backplane Transceiver
Timing Characteristics
(continued)
5-8610 (F)
Note: The total delay from A1 STS1 #1 arriving at LVDS input to RX_TOH_FP is 56 SYS_CLKs and 6 TOH_CLKs. This will vary by ±14
SYS_CLKs, 12 each way for the FIFO alignment, and ±2 SYS_CLKs due to the variability in the clock recovery of the HSI macro.
Figure 19. TOH Output Serial Port Timing (Backplane
->
FPGA)
Table 35. Timing Requirements (TOH Output Serial Port Timing)
Symbol
T
TRANS_SYS
Delay from First A1 LVDS Serial Input to
Transfer to TOH_CLK
T
TRANS_TOH
Delay from Transfer to TOH_CLK to
RX_TOH_FP
Parameter
Min
44
Nom
56
Max
68
Unit
SYS_CLKs
6
TOH_CLKs
RX TOH FP
HDIN
TOH_CLK
1044 bytes SPE
RX TOH
CLK ENA
(INPUT LVDS
SERIAL 622M
DATA)
TOH SERIAL
OUTPUT
ROW #1
ROW #9
36 bytes TOH
1044 bytes SPE
36 bytes TOH
MSbit(7)
OF A1 byte
STS #1
bit 6
OF A1 byte
STS #1
T
TRANS_SYS
T
TRANS_TOH
bit 0
OF A1 byte
STS #1
...
...
...
...
...
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