參數(shù)資料
型號： ORT4622
英文描述： Field-Programmable System Chip (FPSC) Four-Channel x 622 Mbits/s Backplane Transceiver
中文描述： 現(xiàn)場可編程系統(tǒng)芯片（促進(jìn)文化基金）四通道x 622 Mbits /秒背板收發(fā)器
文件頁數(shù)： 34/90頁
文件大?。?/td> 1915K
代理商： ORT4622
ORCAORT4622 FPSC
Four-Channel x 622 Mbits/s Backplane Transceiver
Preliminary Data Sheet
March 2000
34
L Lucent Technologies Inc.
Memory Map
(continued)
Table 10. Memory Map Bit Descriptions
* The error insertion is based on a rising edge detector. As such, the control must be set to value 0 before trying to initiate a second A1/A2
corruption.
The error insertion is based on a rising edge detector. As such, the control must be set to value 0 before trying to initiate a second B1
corruption.
Bit/Register Name(s
)
Bit/ Register
Location (hex)
Register
Type
Default
Value
(hex)
Description
Channel Register Block (Channel A, Channel B, Channel C, Channel D)
(continued)
channel enable/disable control
20, 38, 50, 68 [5]
creg
0
Channel Enable/Disable Control
0
Powerdown channel A/B/C/D CDR
and LVDS I/O can be used with
data_rx_en to 3-state output buses.
1
Functional mode.
To be used as 3-state control for pro-
tection switching on the FPGA data
output.
To be used as 3-state control for TOH
data output. Only channel A enable sig-
nal is brought out.
Transmit Mode of Operation
0
Insert TOH from serial ports.
1
Pass through all TOH.
Other Registers
0
Insert TOH from serial ports.
1
Pass through that particular TOH
byte.
Hi-z control of parallel output bus.
20, 38, 50, 68 [6]
creg
0
Hi-z control of TOH data output.
20 [7]
creg
0
Tx mode of operation
21, 39, 51, 69 [7]
creg
0
Tx E1 F2 E2 source select
Tx S1 M0 source select
Tx K1 K2 source select
Tx D12—D9 source select
Tx D8—D1 source select
A1/A2 error insert command
21, 39, 51, 69 [6]
21, 39, 51, 69 [5]
21, 39, 51, 69 [4]
21, 39, 51, 69 [3:0]
22, 3a, 52, 6a [7:0]
23, 3b, 53, 6b [0]
creg
creg
creg
creg
creg
creg
0
0
0
4’h0
8’h00
0
0
1
Do not insert error.*
Insert error for number of frames in
register hex 0C.*
Do not insert error.
Insert error for one frame in B1 bits
defined by register hex 0F.
The value one in any bit location indi-
cates that STS# is in CONCAT mode.
A 0 indicates that the STS is not in
CONCAT mode, or is the head of a
concat group.
These flag register bits per STS-12
alarm flag, AIS-P flag, and elastic store
overflow flag are the per-channel inter-
rupt status (consolidation) register.
These are per the STS-12 alarm flags
with the corresponding enable/mask
register.
B1 error insert command
23, 3b, 53, 6b [1]
creg
0
0
1
concatindication 12, 9, 6, 3
concatindication 11, 8, 5, 2, 10, 7, 4, 1
24, 3c, 54, 6c [3:0]
25, 3d, 55, 6d [7:0]
sreg
sreg
0
0
per STS-12 alarm flag
AIS-P flag
elastic store overflow flag
enable/mask register [2:0]
FIFO aligner threshold error flag
receiver internal path parity error flag
LOF flag
LVDS link B1 parity error flag
input parallel bus parity error flag
TOH serial input port parity error flag
enable/mask register [5:0]
AIS interrupt flags 12, 9, 6, 3
AIS interrupt flags 11, 8, 5, 2, 10, 7, 4, 1
enable/mask register 12, 9, 6, 3
enable/mask register 11, 8, 5, 2, 10, 7, 4, 1
26, 3e, 56, 6e [0]
26, 3e, 56, 6e [1]
26, 3e, 56, 6e [2]
27, 3f, 57, 6f [2:0]
28, 40, 58, 70 [0]
28, 40, 58, 70 [1]
28, 40, 58, 70 [2]
28, 40, 58, 70 [3]
28, 40, 58, 70 [4]
28, 40, 58, 70 [5]
29, 41, 59, 71 [5:0]
2a, 42, 5a, 72 [3:0]
2b, 43, 5b, 73 [7:0]
2c, 44, 5c, 74 [3:0]
2d, 45, 5d, 75 [7:0]
isreg
isreg
isreg
iereg
iareg
iareg
iareg
iareg
iareg
iareg
iareg
iareg
iareg
iereg
iereg
0
0
0
3’b000
0
0
0
0
0
0
6’h00
4’h0
8’h00
4’h0
8’h00
These are the AIS-P alarm flags with
the corresponding enable/mask
register.
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