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| 型號： | ORT4622 |
| 英文描述： | Field-Programmable System Chip (FPSC) Four-Channel x 622 Mbits/s Backplane Transceiver |
| 中文描述： | 現(xiàn)場可編程系統(tǒng)芯片（促進(jìn)文化基金）四通道x 622 Mbits /秒背板收發(fā)器 |
| 文件頁數(shù)： | 15/90頁 |
| 文件大小： | 1915K |
| 代理商： | ORT4622 |
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Lucent Technologies Inc.
Lucent Technologies Inc.
15
Preliminary Data Sheet
March 2000
ORCA ORT4622 FPSC
Four-Channel x 622 Mbits/s Backplane Transceiver
Backplane Transceiver Core Detailed
Description
(continued)
STM Transmitter (FPGA -> Backplane)
The STM has four STS-12 transmit channels which can
be treated as a single STS-48 channel. In general, the
transmitter circuit receives four byte-wide 77.76 MHz
data from the FPGA, which nominally represents four
STS-12 streams (A, B, C, and D). This data is synchro-
nized to the system (reference) clock, and an 8 kHz
system frame pulse from the FPGA logic. Transport
overhead bytes are then optionally inserted into these
streams, and the streams are forwarded to the HSI. All
byte timing pulses required to isolate individual over-
head bytes (e.g., A1, A2, B1, D1—D3, etc.) are gener-
ated internally based on the system frame pulse
(SYS_FP) received from the FPGA logic. All streams
operate byte-wide at 77.76 MHz in all modes. The TOH
processor operates from 25 MHz to 77.76 MHz and
supports the following TOH signals: A1 and A2 inser-
tion and optional corruption; H1, H2, and H3 pass
transparently; BIP-8 parity calculation (after scram-
bling) and B1 byte insertion and optional corruption
(before scrambling); optional K1 and K2 insert; optional
S1/M0 insert; optional E1/F1/E2 insert; optional section
data communication channel (DCC, D1—D3) and line
data communication channel (DCC, D4—D12) inser-
tion (for intercard communications channel); scram-
bling of outgoing data stream with optional scrambler
disabling; and optional stream disabling.
When the ORT4622 is used in nonnetworking applica-
tions as a generic high-speed backplane data mover,
the TOH serial ports are unused or can be used for
slow-speed off-channel communication between
devices.
Data received on the parallel bus is optionally scram-
bled and transferred to LVDS outputs.
Byte Ordering Information
The core supports quad STS-12 mode of operation on
the input/output ports. STS-48 is also supported when
received in quad STS-12 format. When operating in
quad STS-12 mode, each of the independent byte
streams carries an entire STS-12 within it. Figure 4
reveals the byte ordering of the individual STS-12
streams and for STS-48 operation. Note that the recov-
ered data will always continue to be in the same order
as transmitted.
5-8574 (F)
Figure 4. Byte Ordering of Input/Output Interface in STS-12 Mode
12
24
36
48
9
21
33
45
6
18
30
42
3
15
27
39
11
23
35
47
8
20
32
44
5
17
29
41
2
14
26
38
10
22
34
46
7
19
31
43
4
16
28
40
1
13
25
37
1, 12
2, 12
3, 12
4, 12
1, 9
2, 9
3, 9
4, 9
1, 6
2, 6
3, 6
4, 6
1, 3
2, 3
3, 3
4, 3
1, 11
2, 11
3, 11
4, 11
1, 8
2, 8
3, 8
4, 8
1, 5
2, 5
3, 5
4, 5
1, 2
2, 2
3, 2
4, 2
1, 10
2, 10
3, 10
4, 10
1, 7
2, 7
3, 7
4, 7
1, 4
2, 4
3, 4
4, 4
1, 1
2, 1
3, 1
4, 1
STS-12 A
STS-12 B
STS-12 C
STS-12 D
STS-12 A
STS-12 B
STS-12 C
STS-12 D
STS-48 IN QUAD STS-12 FORMAT
QUAD STS-12
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