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參數(shù)資料
| 型號(hào)： | ORT4622 |
| 英文描述： | Field-Programmable System Chip (FPSC) Four-Channel x 622 Mbits/s Backplane Transceiver |
| 中文描述： | 現(xiàn)場(chǎng)可編程系統(tǒng)芯片（促進(jìn)文化基金）四通道x 622 Mbits /秒背板收發(fā)器 |
| 文件頁數(shù)： | 18/90頁 |
| 文件大小： | 1915K |
| 代理商： | ORT4622 |
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18
Lucent Technologies Inc.
ORCAORT4622 FPSC
Four-Channel x 622 Mbits/s Backplane Transceiver
Preliminary Data Sheet
March 2000
Backplane Transceiver Core Detailed
Description
(continued)
A1/A2 Frame Insert and Testing
The A1 and A2 bytes provide a special framing pattern
that indicates where a STS-1 begins in a bit stream. All
12 A1 bytes of each STS-12 are set to 0xF6, and all 12
A2 bytes of the STS-12 are set to 0x28 when not over-
ridden with an user-specified value for testing.
A1/A2 testing (corruption) is controlled per stream by
the A1/A2 error insert register. When A1/A2 corruption
detection is set for a particular stream, the A1/A2 val-
ues in the corrupted A1/A2 value registers are sent for
the number of frames defined in the corrupted A1/A2
frame count register. When the corrupted A1/A2 frame
count register is set to zero, A1/A2 corruption will con-
tinue until the A1/A2 error insert register is cleared.
On a per-device basis, the A1 and A2 byte values are
set, as well as the number of frames of corruption.
Then, to insert the specified A1/A2 values, each chan-
nel has an enable register. When the enable register is
set, the A1/A2 values are corrupted for the number
specified in the number of frames to corrupt. To insert
errors again, the per-channel fault insert register must
be cleared, and set again. Only the last A1 and the first
A2 are corrupted.
B1 Calculation and Insertion
A bit interleaved parity –8 (BIP-8) error check set for
even parity over all the bits of an STS-1 frame. B1 is
defined for the first STS-1 in an STS-N only. The B1
calculation block computes a BIP-8 code, using even
parity over all bits of the previous STS-12 frame after
scrambling and is inserted in the B1 byte of the current
STS-12 frame before scrambling. Per-bit B1 corruption
is controlled by the force BIP-8 corruption register (reg-
ister address 0F). For any bit set in this register, the
corresponding bit in the calculated BIP-8 is inverted
before insertion into the B1 byte position. Each stream
has an independent fault insert register that enables
the inversion of the B1 bytes. B1 bytes in all other STS-
1s in the stream are filled with zeros.
Stream Disable
When disabled via the appropriate bit in the stream
enable register, the prescrambled data for a stream is
set to all ones, feeding the HSI. The HSI macro is pow-
ered down on a per-stream basis, as are its LVDS out-
puts.
Scrambler
The data stream is scrambled using a frame synchro-
nous scrambler of sequence length 127. The scram-
bling function can be disabled by software. The
generating polynomial for the scrambler is 1 + x
6
+ x
7
.
This polynomial conforms to the standard SONET
STS-12 data format. The scrambler is reset to 1111111
on the first byte of the SPE (byte following the Z0 byte
in the twelfth STS-1). That byte and all subsequent
bytes to be scrambled are exclusive-ORed, with the
output from the byte-wise scrambler. The scrambler
runs continuously from that byte on throughout the
remainder of the frame. A1, A2, J0, and Z0 bytes are
not scrambled.
System Frame Pulse and Line Frame Pulse
System frame pulse (for transmitter) and line frame
pulse (for receiver) are generated in FPGA logic. A1/A2
framing is used on the link for locating the 8 kHz frame
location. All frames sent to the FPGA are aligned to the
FPGA frame pulse LINE_FP which is provided by the
FPGA to the STM macro. All frames sent from the
FPGA to the STM will be aligned to the frame pulse
SYS_FP that is supplied to the STM macro. In either
directions, system frame pulse and line frame pulse are
active for one system clock cycle, indicating the loca-
tion of A1 byte of STS#1. They are common to all four
channels.
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