參數(shù)資料
型號: ORCAORT4622
英文描述: Field-Programmable System Chip (FPSC) Four-Channel x 622 Mbits/s Backplane Transceiver
中文描述: 現(xiàn)場可編程系統(tǒng)芯片(促進(jìn)文化基金)四通道x 622 Mbits /秒背板收發(fā)器
文件頁數(shù): 55/90頁
文件大?。?/td> 1915K
代理商: ORCAORT4622
Lucent Technologies Inc.
Lucent Technologies Inc.
55
Preliminary Data Sheet
March 2000
ORCA ORT4622 FPSC
Four-Channel x 622 Mbits/s Backplane Transceiver
Timing Characteristics
(continued)
5-8612 (F)
Notes:
The CPU interface can be bit stream selected either from device I/O or FPGA interface. The timing diagram applies to both interfaces, but not to
the FPGA MPI block.
The time delay between the advanced SYS_CLK and the distributed SYS_CLK used to sample CS_N is of no consequence. However, the
path delay of CS_N from pad to where is it sampled by SYS_CLK must be minimized.
The calculated delays assume a 100 pF loading on the DB pins.
Figure 21. CPU Read Transaction
Table 37. Timing Requirements (CPU Read Transaction)
Symbol
T
PULSE
T
ADDR_MAX
Parameter
Min
5
Max
5
Unit
ns
ns
Minimum Pulse Width for CS_N
Maximum Time from Negative Edge of
CS_N to ADDR Valid
Maximum Time from Negative Edge of
CS_N to RD_WR_N Falling
Maximum Time from Negative Edge of
CS_N to Data Valid on DB Port
Maximum Time from Rising Edge of
CS_N to DB Port Going HI-Z
Minimum Time Between a Read Cycle
(falling edge of CS_N) and Any Other Transaction
(read or write at falling edge of CS_N)
T
RD_WR_MAX
5
ns
T
DATA_MAX
56
ns
T
HIZ_MAX
12
ns
T
ACCESS_MIN
60
ns
DATA VALID
T
ACCESS_MIN
T
PULSE
T
DATA_MAX
CPU_CS_N
(CS_N)
CPU_RD_WR_N
(RD_WR_N)
CPU_ADDR[6:0]
(ADDR[6:0])
CPU_DATA[7:0]
(DB[7:0])
T
HIZ_MAX
T
ADDR_MAX
T
RD_WR_MAX
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