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| 型號： | ORCAORT4622 |
| 英文描述： | Field-Programmable System Chip (FPSC) Four-Channel x 622 Mbits/s Backplane Transceiver |
| 中文描述： | 現(xiàn)場可編程系統(tǒng)芯片（促進(jìn)文化基金）四通道x 622 Mbits /秒背板收發(fā)器 |
| 文件頁數(shù)： | 26/90頁 |
| 文件大小： | 1915K |
| 代理商： | ORCAORT4622 |
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ORCAORT4622 FPSC
Four-Channel x 622 Mbits/s Backplane Transceiver
Preliminary Data Sheet
March 2000
26
L Lucent Technologies Inc.
Memory Map
Definition of Register Types
There are six structural register elements: sreg, creg, preg, iareg, isreg, and iereg. There are no mixed registers in
the chip. This means that all bits of a particular register (particular address) are structurally the same.
Table 8. Structural Register Elements
Registers Access and General Description
The memory map comprises three address blocks:
I
Generic register block: ID, revision, scratch pad, lock, FIFO alignment, and reset registers.
I
Device register block: control and status bits, common to the four channels.
I
Channel register blocks: each of the four channels have an address block. The four address blocks have the
exact same structure with a constant address offset between channel register blocks.
All registers are write-protected by the lock register, except for the scratch pad register. The lock register is a 16-bit
read/write register. Write access is given to registers only when the key value 0xA001 is present in the lock register.
An error flag will be set upon detecting a write access when write permission is denied. The default value is
0x0000.
After powerup reset or soft reset, unused register bits will be read as zeros. Unused address locations are also
read as zeros. Write only register bits will be read as zeros. The detailed information on register access and func-
tion are described on the tables, memory map, and memory map bit description.
Element
sreg
Register
Status Register A status register is read only, and, as the name implies, is used to convey the status
information of a particular element or function of the ORT4622 core. The reset value
of an sreg is really the reset value of the particular element or function that is being
read. In some cases, an sreg is really a fixed value. An example of which is the fixed
ID and revision registers.
Control Register A control register is read and writable memory element inside core control. The
value of a creg will always be the value written to it. Events inside the ORT4622 core
cannot effect creg value. The only exception is a soft reset, in which case the creg
will return to its default value. The control register have default values as defined in
the default value column of Table 9.
Pulse Register
Each element, or bit, of a pulse register is a control or event signal that is asserted
and then deasserted when a value of one is written to it. This means that each bit is
always of value 0 until it is written to, upon which it is pulsed to the value of one and
then returned to a value of 0. A pulse register will always have a read value of 0.
Interrupt Alarm
Register
produced in the ORT4622 core, its occurrence is latched by its associated iareg bit.
To clear a particular iareg bit, a value of one must be written to it. In the ORT4622
core, all isreg reset values are 0.
Interrupt Status
Register
consolidation of lower level interrupt alarms and/or isreg bits from other registers. A
direct result of the fact that each bit of the isreg is a logical-OR function means that it
will have a read value of one if any of the consolidation signals are of value one, and
will be of value 0 if and only if all consolidation signals are of value 0. In the
ORT4622 core, all isreg default values are 0.
Interrupt Enable
Register
is set to value one, then the event is allowed to propagate to the next higher level of
consolidation. If this bit is set to zero, then the associated iareg or isreg bit can still
be asserted but an alarm will not propagate to the next higher level. An interrupt
enable bit is an interrupt mask bit when it is set to value 0.
Description
creg
preg
iareg
Each bit of an interrupt alarm register is an event latch. When a particular event is
isreg
Each bit of an interrupt status register is physically the logical-OR function. It is a
ereg
Each bit of a status register or alarm register has an associated enable bit. If this bit
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