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參數(shù)資料
| 型號： | ORCAORT4622 |
| 英文描述： | Field-Programmable System Chip (FPSC) Four-Channel x 622 Mbits/s Backplane Transceiver |
| 中文描述： | 現(xiàn)場可編程系統(tǒng)芯片（促進文化基金）四通道x 622 Mbits /秒背板收發(fā)器 |
| 文件頁數(shù)： | 13/90頁 |
| 文件大?。?/td> | 1915K |
| 代理商： | ORCAORT4622 |
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Lucent Technologies Inc.
Lucent Technologies Inc.
13
Preliminary Data Sheet
March 2000
ORCA ORT4622 FPSC
Four-Channel x 622 Mbits/s Backplane Transceiver
Generic Backplane Transceiver
Application
The combination of ORT4622 and soft IP cores pro-
vides a generic data moving solution for non-SONET
applications. There is no requirement for SONET
knowledge to the users. All that is needed is to supply
the embedded core interface with data, clock, and a
8 kHz frame pulse. The provision registers may also
need to be set up, and this can be done through either
the FPGA MPI or in a state machine in the FPGA sec-
tion (VHDL code available from Lucent).
The 8 kHz frame pulse must be supplied to the
SYS_FP signal. For generic applications, the frame
pulse can be created in FPGA logic from the
77.76 MHz SYS_CLK using a simple resettable
counter (the frame pulse should only be high for one
cycle of the SYS_CLK). A VHDL core that automati-
cally provides the 8 kHz frame pulse is available from
Lucent. Byte-wide data is then sent to each of the
transmit channels as follows: the first 36 bytes trans-
ferred will be invalid data (replaced by overhead),
where the first byte is sent on the rising edge of
SYS_CLK when SYS_FP is high. The next 1044 byte
positions can be filled with valid data. This will repeat a
total of nine times (36 invalid bytes followed by 1044
valid bytes) at which time the next 8 kHz frame pulse
will be found. Thus, 87 out of 90 (96.7%) of the data
bytes sent are valid user data.
On the receive side, an 8 kHz pulse must again be sup-
plied to SYS_FP. In this case, however, only the signal
DATA_RX*_SPE must be monitored for each channel,
where a high value on this signal means valid data.
Again 87 out 90 bytes received (96.7%) will be valid
data.
In order to provide an easy user interface to transfer
arbitrary data streams through the ORT4622, Lucent
provides a soft Intellectual Property (IP) core called the
protocol independent framer, or PI-Framer. This block
transfers user format to the one described above and
allows for smoothing/rate transfer of this user data.
This framer works with a single channel at 622 Mbits/s,
two channels at 1.25 Gbits/s, or across four channels
at 2.5 Gbits/s.
Backplane Transceiver Core Detailed
Description
HSI Macro
The high-speed interface (HSI) provides a physical
medium for high-speed asynchronous serial data trans-
fer between the ORT4622 and other devices. The
devices can be mounted on the same board or
mounted on different boards and connected through
the shelf backplane. The 622 Mbits/s CDR macro is a
four-channel clock phase select (CPS) and data retime
function with serial-to-parallel demultiplexing for the
incoming data stream and parallel-to-serial multiplexing
for outgoing data. The HSI macro consists of three
functionally independent blocks: receiver, transmitter,
and PLL synthesizer as shown in Figure 3.
The PLL synthesizer block receives a 77.76 MHz refer-
ence clock at its input, and provides a phase-locked
622.08 MHz clock to the transmitter block and phase
control signal to the receiver block. The PLL synthe-
sizer block is a common asset shared by four receive
and transmit channels.
The HSI receiver receives four channels of differential
622.08 Mbits/s serial data without clock at its LVDS
receive inputs. The received data must be scrambled,
conforming to SONET STS-12 and SDH STM-4 data
formats using either a PN7 or PN9 sequence. The PN7
characteristic polynomial is 1 + x
6
+ x
7
, and PN9 char-
acteristic polynomial is 1 + x
4
+ x
9
. The ORT4622 sup-
plies a default scrambler using the PN7 sequence. The
clock phase select and data retime (CPS/DR) module
performs a clock recovery and data retiming function
by using phase control information. The resultant
622.08 Mbits/s data and clock are then passed to the
deserializer module, which performs serial-to-parallel
conversion and provides a 77.76 Mbits/s parallel data
and clock at its output.
The HSI transmitter receives four channels of
77.76 Mbits/s parallel data that is synchronous to the
reference clock at its inputs. The serializer performs a
parallel-to-serial conversion using a 622.08 MHz clock
provided by the PLL/synthesizer block. The
622 Mbits/s serial data streams are then transmitted
through the LVDS drivers.
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