參數(shù)資料
型號(hào)： OMAP5910(DSP)
英文描述： Dual-Core Processor
中文描述： 雙核處理器
文件頁數(shù)： 33/160頁
文件大?。?/td> 1997K
代理商： OMAP5910(DSP)
Introduction
21
August 2002 Revised August 2003
SPRS197B
Table 24. Signal Description (Continued)
GDY
BALL
SIGNAL
TYPE
DESCRIPTION
GZG
BALL
EMIFF SDRAM Interface (Continued)
SDRAM.A[12:0]
G10,
H10,
C11,
D11,
G11,
C12,
D12,
H11,
C13,
D13,
G12,
C14,
B14
C8,
B9,
E9,
A8,
C10,
F9,
D9,
A9,
D10,
C11,
B10,
A10,
B11
SDRAM address bus. Provides row and column address information to the
SDRAM memory as well as MRS command data. SDRAM.A[10] also serves as a
control signal to define specific commands to SDRAM memory.
O/Z
EMIFS FLASH and Asynchronous Memory Interface
FLASH.WP
V4
R3
EMIFS write protect. Active-low output for hardware write protection feature on
standard memory devices.
O/Z
FLASH.WE
W2
P2
EMIFS write enable. Active-low write enable output for Flash or SRAM memories
or asynchronous devices.
O/Z
FLASH.RP
W1
T2
EMIFS power down or reset output (Intel
flash devices)
O/Z
FLASH.OE
U4
N3
EMIFS output enable. Active-low output enable output for Flash or SRAM
memories or asynchronous devices.
O/Z
FLASH.D[15:0]
V3,
T4,
U3,
U1,
P8,
T3,
T2,
R4,
R3,
R2,
P7,
P4,
P2,
N7,
N2,
N4
U2,
T1,
N2,
R1,
M3,
P1,
N1,
N4,
M5,
M4,
M2,
M1,
L6,
L4,
K3,
L5
EMIFS data bus. Bidirectional 16-bit data bus used to transfer read and write data
during EMIFS accesses.
I/O/Z
FLASH.CLK
N3
K4
EMIFS clock. Clock output that is active during synchronous modes of EMIFS
operation for synchronous burst Flash memories.
O/Z
FLASH.CS3
N8
L1
appropriate address is decoded internal to the device. Each chip select decodes a
32M-byte region of memory space.
O/Z
FLASH.CS2
M4
K5
EMIFS chip selects. Active-low chip-select outputs that become active when the
FLASH.CS1
M3
K1
FLASH.CS0
M7
J2
FLASH.BE[1:0]
M8,
L3
J1,
J5
EMIFS byte enables. Active-low byte enable signals used to perform byte-wide
accesses to memories or devices that support byte enables.
O/Z
FLASH.ADV
L4
H1
EMIFS address valid. Active-low control signal used to indicate a valid address is
present on the FLASH.A[24:1] bus.
O/Z
FLASH.BAA
M4
K5
EMIFS burst advance acknowledge. Active-low control signal used with Advanced
Micro Devices
burst Flash. FLASH.BAA is multiplexed with FLASH.CS2.
O/Z
I = Input, O = Output, Z = High-Impedance
All core voltage supplies should be tied to the same voltage level (within 0.3 V). During system prototyping phases, it may be useful to maintain
a capability for independent measurement of core supply currents to facilitate power optimization experiments.
§See Sections 5.6.1 and 5.6.2 for special VSS considerations with oscillator circuits.
Intel is a registered trademark of Intel Corporation.
Advanced Micro Devices is a trademark of Advanced Micro Devices, Inc.
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