參數(shù)資料
型號： OMAP5910(DSP)
英文描述： Dual-Core Processor
中文描述： 雙核處理器
文件頁數(shù)： 147/160頁
文件大?。?/td> 1997K
代理商： OMAP5910(DSP)
Electrical Specifications
135
August 2002 Revised August 2003
SPRS197B
5.12 LCD Controller Timings
Table 527 assumes testing over recommended operating conditions (see Figure 527 and Figure 528).
Table 527. LCD Controller Switching Characteristics
NO.
PARAMETER
MIN
MAX
UNIT
L1
td(CLKHHSV)
td(CLKLHSV)
td(CLKHVSV)
td(CLKLVSV)
td(CLKHPV)
td(CLKHPIV)
td(CLKLPV)
td(CLKLPIV)
td(CLKLACV)
td(CLKLACV)
Delay time, LCD.PCLK high to LCD.HS transition
1
11
ns
L2
Delay time, LCD.PCLK low to LCD.HS transition
1
11
ns
L3
Delay time, LCD.PCLK high to LCD.VS transition
1
11
ns
L4
Delay time, LCD.PCLK low to LCD.VS transition
1
11
ns
L5
Delay time, LCD.PCLK high to pixel data valid (LCD.P[15:0])
11
ns
L6
Delay time, LCD.PCLK high to pixel data invalid (LCD.P[15:0])
1
ns
L7
Delay time, LCD.PCLK low to pixel data valid (LCD.P[15:0])
11
ns
L8
Delay time, LCD.PCLK low to pixel data invalid (LCD.P[15:0])
1
ns
L9
Delay time, LCD.PCLK high to LCD.AC transition
1
5+P
5+P
ns
L10
Delay time, LCD.PCLK low to LCD.AC transition
1
ns
Although timing diagrams illustrate the logical function of the TFT mode, static timings apply to all supported modes of operation. Likewise,
LCD.HS, LCD.VS, and LCD.AC are shown as active-low, but each may optionally be configured as active-high.
P = period of internal undivided pixel clock
LCD.PCLK
LCD.VS
LCD.P[15:0]
LCD.AC
LCD.HS
L4
L9
L5
D1
D2
D3
Dn
L6
L9
L4
L2
L2
HSW
VSW
VFP
HFP
HBP
PPL
Delays for HSW (LCD.HS Width), VSW (LCD.VS Width), VFP (Vertical Front Porch), HFP (Horizontal Front Porch), HBP (Horizontal Back Porch)
and PPL (Pixels per Line) are programmable in number of LCD.PCLK cycles via the LCD configuration registers.
Figure 527. TFT Mode (LCD.HS/LCD.VS on Falling and LCD.Px on Rising LCD.PCLK)
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