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參數(shù)資料
| 型號： | MT90401AB1 |
| 廠商： | ZARLINK SEMICONDUCTOR INC |
| 元件分類： | 數(shù)字傳輸電路 |
| 英文描述： | SONET/SDH System Synchronizer |
| 中文描述： | ATM/SONET/SDH SUPPORT CIRCUIT, PQFP80 |
| 封裝： | 14 X 14 MM, 1.40 MM HEIGHT, LEAD FREE, MS-026BEC, LQFP-80 |
| 文件頁數(shù)： | 26/38頁 |
| 文件大?。?/td> | 650K |
| 代理商： | MT90401AB1 |
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MT90401
Data Sheet
26
Zarlink Semiconductor Inc.
0EH
Reserved
Read
Only
0FH (Table 11)
Identification Word
Read
Only
ID7-0
10H
Reserved
Read/
Write
Set all bits to zero.
Bit
Name
Functional Description
7
RSEL
Reference Select
. A zero selects the PRI (primary) reference source as the input
reference signal and a one selects the SEC (secondary) reference. Switching between
reference clocks operating at 8 kHz, 1.544 MHz and 2.048 MHz can be done at any time
and without any special setup procedures. However it is recommended that the switching
of the 19.44 MHz references will be performed by forcing PLL temporary into Holdover
mode (MS2,MS1=01) to prevent excessive phase accumulation in the internal controller.
The PLL can be switched back to Normal mode (MS2,MS1= 00) 250 us after the new
input reference has been selected.
6 - 5
FS2-1
Frequency Select 2 - 1
. These bits select which of four possible frequencies (8 kHz,
1.544 MHz, 2.048 MHz or 19.44 MHz) may be input to the PRI and SEC inputs.
FS2 - 0, FS1 - 0 = 19.44 MHz
FS2 - 0, FS1 - 1 = 8 kHz.
FS2 - 1, FS1 - 0 = 1.544 MHz.
FS2 - 1, FS1 - 1 = 2.048 MHz.
When “19.44 MHz” reference clock option is selected, a loss of 19.44 MHz clock or a
larger than 30000 ppm frequency deviation may create a frequency step exceeding ±4.6
ppm upon return from Auto-Holdover mode. This may result in a lock time that is longer
than normally guaranteed.
4 - 3
MS2-1
Mode Select 2 - 1
: These bits select the PLL state of operation.
MS2 - 0, MS1 - 0 = Normal.
MS2 - 0, MS1 - 1 = Holdover.
MS2 - 1, MS1 - 0 = Freerun.
MS2 - 1, MS1 - 1 = Reserved.
2
SONET/SDH
SONET / SDH
. Set to one to move the loop filter corner frequency to 70 millihertz and
limit the phase slope to 885 ns per second as per SONET requirements. Set to zero to
move the corner frequency to 1.1 Hz and limit the phase slope to 53 ns per 1.326 ms.
1
FLOCK
Fast Lock
. Set to one to allow the PLL to lock faster than normal to the input reference.
During the time that FLOCK is one, the wander generation of the PLL is, of necessity,
compromised. Set to zero for normal operation.
Table 6 - Control Register 1 (Address 00H - Read/Write)
Control and Status Registers (continued)
Address
(A
6
A
5
A
4
A
3
A
2
A
1
A
0
)
Register
Read/
Write
Function
Table 5 - Register Map (continued)
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