參數(shù)資料
型號(hào)： MT90401AB1
廠商： ZARLINK SEMICONDUCTOR INC
元件分類： 數(shù)字傳輸電路
英文描述： SONET/SDH System Synchronizer
中文描述： ATM/SONET/SDH SUPPORT CIRCUIT, PQFP80
封裝： 14 X 14 MM, 1.40 MM HEIGHT, LEAD FREE, MS-026BEC, LQFP-80
文件頁(yè)數(shù)： 10/38頁(yè)
文件大?。?/td> 650K
代理商： MT90401AB1
MT90401
Data Sheet
10
Zarlink Semiconductor Inc.
1.0 Functional Description
The MT90401 is a SONET/SDH System Synchronizer, providing timing (clock) and synchronization (frame) signals
to interface circuits for Digital Telecommunications Transmission links. Figure 1 is a functional block diagram which
is described in the following sections.
1.1 Reference Select MUX Circuit
The MT90401 accepts two simultaneous reference input signals and operates on their falling edges. Either the
primary reference (PRI) signal or the secondary reference (SEC) signal can be selected as input to the TIE
Corrector Circuit. The selection is based on the Control, Mode and Reference Selection of the device. See Table 1
and Table 4.
1.2 Frequency Select MUX Circuit
The MT90401 operates with one of four possible input reference frequencies (8 kHz, 1.544 MHz, 2.048 MHz or
19.44 MHz). The frequency select inputs, FS1 and FS2, which come from pins in hardware mode and control bits in
microport mode determine which of the four frequencies may be used at the reference inputs (PRI and SEC). Both
inputs must have the same frequency applied to them. A reset (RST) must be performed after every frequency
select input change. See Table 1 - Input Frequency Selection.
1.3 Time Interval Error (TIE) Corrector Circuit
The TIE corrector circuit, when enabled, prevents a step change in phase on the input reference signals (PRI or
SEC) from causing a step change in phase at the input of the DPLL block of Figure 1.
During reference input rearrangement, such as during a switch from the primary reference (PRI) to the secondary
reference (SEC), a step change in phase on the input signals will occur. A phase step at the input of the DPLL
would lead to unacceptable phase changes in the output signal.
As shown in Figure 3, the TIE Corrector Circuit receives one of the two reference (PRI or SEC) signals, passes the
signal through a programmable delay line, and uses this delayed signal as an internal virtual reference, which is
input to the DPLL. Therefore, the virtual reference is a delayed version of the selected reference. During a switch
from one reference to the other, the State Machine first changes the mode of the device from Normal to Holdover. In
Holdover Mode, the DPLL no longer uses the virtual reference signal, but generates an accurate clock signal using
storage techniques. The Compare Circuit then measures the phase delay between the current phase (feedback
signal) and the phase of the new reference signal. This delay value is passed to the Programmable Delay Circuit
(See Figure 3). The new virtual reference signal is now at the same phase position as the previous reference signal
would have been if the reference switch had not taken place. The State Machine then returns the device to Normal
Mode.
FS2
FS1
Input Frequency
0
0
19.44 MHz
See FS2 and FS1 bit description
in Table 6 - Control Register 1
(Address 00H - Read/Write)
0
1
8 kHz
1
0
1.544 MHz
1
1
2.048 MHz
Table 1 - Frequency Selection
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