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參數(shù)資料
| 型號： | MT90401AB1 |
| 廠商： | ZARLINK SEMICONDUCTOR INC |
| 元件分類： | 數(shù)字傳輸電路 |
| 英文描述： | SONET/SDH System Synchronizer |
| 中文描述： | ATM/SONET/SDH SUPPORT CIRCUIT, PQFP80 |
| 封裝： | 14 X 14 MM, 1.40 MM HEIGHT, LEAD FREE, MS-026BEC, LQFP-80 |
| 文件頁數(shù)： | 24/38頁 |
| 文件大?。?/td> | 650K |
| 代理商： | MT90401AB1 |
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MT90401
Data Sheet
24
Zarlink Semiconductor Inc.
0.02 ppm is the accuracy of Holdover Mode
50 ns is the maximum phase continuity of the MT90401 from Normal Mode to Holdover Mode
200 ns is the maximum phase continuity of the MT90401 from Holdover Mode to Normal Mode (with or
without TIE Corrector Circuit)
When the same ten Normal to Holdover to Normal mode changes occur with TIE disabled, the overall MTIE will
only be 250 ns. There would be no accumulated phase change, since the input to output phase is re-aligned after
every Holdover to Normal state change.
5.3 C155 clock generation and LVDS output drivers
The MT90401 provides a 155.52 MHz clock that is frequency locked to the internally generated 19.44 MHz clock.
The locking of both clocks is achieved by the internal analog PLL that multiplies the 19.44 MHz clock eight times.
This C155 clock is output on pins C155P and C155N in LVDS format. The LVDS offset voltage Vos is set by
applying an external 1.25 V reference voltage to the Vref input (pin 33). This pin can be connected to a common
1.25 V voltage reference that may exist on the customer board or alternatively can be generated by a simple
voltage divider as it is shown in Figure 13 - LVDS Voltage Offset Vos Generation Circuit. To ensure proper operation
of LVDS drivers, the decoupling capacitor must be placed very close to the MT90401 package.
Figure 13 - LVDS Voltage Offset Vos Generation Circuit
5.4 Microport
If the HW pin is tied low, an 8 bit Motorola microprocessor may be used to control the PLL and report on the device
status. In this case the control pins SONET/SDH, RSEL, MS1, MS2, FS1, FS2, and FLOCK are unused and they
are replaced by the control bits SONET/SDH, RSEL, MS1, MS2, FS1, FS2, FLOCK. The input pin PCCi remains in
use. The output pins LOCK, HOLDOVER, SECOOR, PRIOOR function whether the device is in microprocessor
mode or hardware mode, but these signals are also available in Status Register 1. The microport provides
additional functionality not available in hardware.
Phasehold
Phasestate
Phase10
0.02ppm
2s
×
40ns
=
=
50ns
200ns
250ns
=
+
=
10
250ns
40ns
+
(
)
×
2.9us
=
=
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