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參數(shù)資料
| 型號： | MT9040AN |
| 廠商： | ZARLINK SEMICONDUCTOR INC |
| 元件分類： | 通信及網(wǎng)絡 |
| 英文描述： | T1/E1 Synchronizer |
| 中文描述： | SPECIALTY TELECOM CIRCUIT, PDSO48 |
| 封裝： | 0.300 INCH, MO-118AA, SSOP-48 |
| 文件頁數(shù)： | 1/27頁 |
| 文件大小： | 424K |
| 代理商： | MT9040AN |
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1
Zarlink Semiconductor Inc.
Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc.
Copyright 2003, Zarlink Semiconductor Inc. All Rights Reserved.
Features
Supports AT&T TR62411 and Bellcore GR-1244-
CORE and Stratum 4 timing for DS1 interfaces
Supports ETSI ETS 300 011, TBR 4, TBR 12 and
TBR 13 timing for E1 interfaces
Selectable 19.44 MHz, 1.544MHz, 2.048MHz or
8kHz input reference signals
Provides C1.5, C2, C4, C6, C8, C16, and C19
(STS-3/OC3 clock divided by 8) output clock
signals
Provides 5 different styles of 8 KHz framing
pulses
Attenuates wander from 1.9Hz
Fast lock mode
JTAG Boundary Scan
Applications
Synchronization and timing control for multitrunk
T1 and E1 systems
ST-BUS clock and frame pulse source
Description
The MT9040 T1/E1 System Synchronizer contains a
digital phase-locked loop (DPLL), which provides timing
and synchronization signals for T1 and E1 primary rate
transmission links.
The MT9040 generates ST-BUS clock and framing
signals that are phase locked to either a 19.44 MHz,
2.048MHz, 1.544MHz, or 8kHz input reference.
The MT9040 is compliant with AT&T TR62411 and
Bellcore GR-1244-CORE, Stratum 4; and ETSI ETS
300 011. It will meet the jitter/wander tolerance, jitter
transfer, intrinsic jitter, frequency accuracy and capture
range for these specifications.
November 2003
Ordering Information
MT9040AN 48 pin SSOP
-40
°
C to +85
°
C
MT9040
T1/E1 Synchronizer
Data Sheet
Figure 1 - Functional Block Diagram
IEEE
1149.1a
Feedback
Control State Machine
DPLL
Frequency
Select
MUX
Input
Impairment
Monitor
Output
Interface
Circuit
MS
FS1
FS2
TCK
TDI
TMS
TRST
RST
VDD
VSS
C1.5o
C2o
C4o
C6o
C19o
C8o
C16o
F0o
F8o
F16o
RSP
TSP
OSCo
OSCi
Master Clock
TDO
FLOCK
LOCK
IM
REF
Zarlink Semiconductor US Patent No. 5,602,884, UK Patent No. 0772912,
France Brevete S.G.D.G. 0772912; Germany DBP No. 69502724.7-08
相關PDF資料 |
PDF描述 |
|---|---|
| MT9043 | T1/E1 System Synchronizer |
| MT9043AN | T1/E1 System Synchronizer |
| MT9043AN48PINSSOP | T1/E1 System Synchronizer |
| MT9045 | T1/E1/OC3 System Synchronizer |
| MT9045AN | T1/E1/OC3 System Synchronizer |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| MT9040AN1 | 制造商:Microsemi Corporation 功能描述:FRAMER E1 /T1 3.3V 48SSOP - Rail/Tube |
| MT9040ANR1 | 制造商:Microsemi Corporation 功能描述:FRAMER E1 /T1 3.3V 48SSOP - Tape and Reel |
| MT9041 | 制造商:MITEL 制造商全稱:Mitel Networks Corporation 功能描述:Multiple Output Trunk PLL |
| MT9041AP | 制造商:Microsemi Corporation 功能描述:WAN/PLL 制造商:Zarlink Semiconductor Inc 功能描述:WAN/PLL |
| MT9041B | 制造商:MITEL 制造商全稱:Mitel Networks Corporation 功能描述:T1/E1 System Synchronizer |
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