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64Mb: x32 SDRAM
64MSDRAMx32_5.p65 – Rev. B; Pub. 6/02
Micron Technology, Inc., reserves the right to change products or specifications without notice.
2002, Micron Technology, Inc.
64Mb: x32
SDRAM
READ – DQM OPERATION
1
tCH
tCL
tCK
tRCD
CAS Latency
CKE
CLK
DQ
A10
tCMS
ROW
BANK
ROW
BANK
DON’T CARE
UNDEFINED
tAC
LZ
D
OUT
m
tHZ
tOH
D
OUT
m
+ 3
tHZ
D
OUT
m
+ 2
t
LZ
t
tCMH
COMMAND
NOP
NOP
NOP
ACTIVE
NOP
READ
NOP
NOP
NOP
tAC
tOH
tAC
tOH
tAH
tAS
tCMS
tCMH
tAH
tAS
tAH
tAS
tCKH
tCKS
ENABLE AUTO PRECHARGE
DISABLE AUTO PRECHARGE
COLUMN
m
2
T0
T1
T2
T4
T3
T5
T6
T7
T8
BA0, BA1
DQM 0-3
A0-A9
NOTE:
1. For this example, the CAS latency = 2.
2. A8 and A9 = “Don’t Care.”
*CAS latency indicated in parentheses.
-5
-6
-7
SYMBOL*
t
CKH
t
CKS
t
CMH
t
CMS
t
HZ (3)
t
HZ (2)
t
HZ (1)
t
LZ
t
OH
t
RCD
MIN
1
1.5
1
1.5
MAX
MIN
1
1.5
1
1.5
MAX
MIN
1
2
1
2
MAX
UNITS
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
4.5
-
-
5
5.5
8
17
7.5
17
1
1
2
18
1
1.5
15
2.5
20
TIMING PARAMETERS
-5
-6
-7
SYMBOL*
t
AC (3)
t
AC (2)
t
AC (1)
t
AH
t
AS
t
CH
t
CL
t
CK (3)
t
CK (2)
t
CK (1)
MIN
MAX
4.6
-
-
MIN
MAX
5.5
7.5
17
MIN
MAX
5.5
8
17
UNITS
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
1
1
1
2
1.5
2
2
5
-
-
1.5
2.5
2.5
6
10
20
2.75
2.75
7
10
20