參數(shù)資料
型號(hào)： MT48LC2M32B2
廠商： Micron Technology, Inc.
英文描述： SYNCHRONOUS DRAM
中文描述： 同步DRAM
文件頁(yè)數(shù)： 33/53頁(yè)
文件大?。?/td> 1818K
代理商： MT48LC2M32B2
33
64Mb: x32 SDRAM
64MSDRAMx32_5.p65 – Rev. B; Pub. 6/02
Micron Technology, Inc., reserves the right to change products or specifications without notice.
2002, Micron Technology, Inc.
64Mb: x32
SDRAM
ELECTRICAL CHARACTERISTICS AND RECOMMENDED AC OPERATING CONDITIONS
(Notes: 5, 6, 8, 9, 11; notes appear on page 35)
AC CHARACTERISTICS
PARAMETER
Access time from CLK
(pos. edge)
-6
-7
SYMBOL
t
AC (3)
t
AC (2)
t
AC (1)
t
AH
t
AS
t
CH
t
CL
t
CK (3)
t
CK (2)
t
CK (1)
t
CKH
t
CKS
t
CMH
t
CMS
t
DH
t
DS
t
HZ (3)
t
HZ (2)
t
HZ (1)
t
LZ
t
OH
t
RAS
t
RC
t
RFC
t
RCD
t
REF
t
RP
t
RRD
t
T
t
WR
MIN
MAX
5.5
7.5
17
MIN
MAX
5.5
8
17
UNITS NOTES
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ms
ns
ns
ns
t
CK
CL = 3
CL = 2
CL = 1
Address hold time
Address setup time
CLK high-level width
CLK low-level width
Clock cycle time
1
1
2
1.5
2.5
2.5
6
10
20
1
1.5
1
1.5
1
1.5
2.75
2.75
7
10
20
1
2
1
2
1
2
CL = 3
CL = 2
CL = 1
23
23
23
CKE hold time
CKE setup time
CS#, RAS#, CAS#, WE#, DQM hold time
CS#, RAS#, CAS#, WE#, DQM setup time
Data-in hold time
Data-in setup time
Data-out high-impedance time
CL = 3
CL = 2
CL = 1
5.5
7.5
17
5.5
8
17
10
10
10
Data-out low-impedance time
Data-out hold time
ACTIVE to PRECHARGE command
ACTIVE to ACTIVE command period
AUTO REFRESH period
ACTIVE to READ or WRITE delay
Refresh period (4,096 rows)
PRECHARGE command period
ACTIVE bank
a
to ACTIVE bank
b
command
Transition time
WRITE recovery time
1
2
42
60
60
18
1
2.5
42
70
70
20
120k
120k
64
64
18
12
0.3
1CLK+
6ns
12ns
70
20
14
0.3
1CLK+
7ns
14ns
70
25
7
24
1.2
1.2
ns
ns
28
20
Exit SELF REFRESH to ACTIVE command
t
XSR
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MT48LC2M32B2-6G 制造商:Micron Technology Inc 功能描述:
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