參數(shù)資料
型號： MSC8144VT800A
廠商： Freescale Semiconductor
文件頁數(shù)： 76/80頁
文件大?。?/td> 0K
描述： IC DSP QUAD 800MHZ 783FCBGA
標準包裝： 1
系列： StarCore
類型： SC3400 內(nèi)核
接口： 以太網(wǎng)，I²C，SPI，TDM，UART，UTOPIA
時鐘速率： 800MHz
非易失內(nèi)存： 外部
芯片上RAM： 10.5MB
電壓 - 輸入/輸出： 3.30V
電壓 - 核心： 1.00V
工作溫度： 0°C ~ 90°C
安裝類型： 表面貼裝
封裝/外殼： 783-BBGA，F(xiàn)CBGA
供應(yīng)商設(shè)備封裝： 783-FCPBGA（29x29）
包裝： 托盤
MSC8144 Quad Core Digital Signal Processor Data Sheet, Rev. 16
Revision History
Freescale Semiconductor
78
7
Revision History
Table 66 provides a revision history for this data sheet.
Table 66. Document Revision History
Rev.
Date
Description
0
Feb. 2007
Initial public release.
1
Apr. 2007
Adds new I/O multiplexing mode 7 that supports POS functionality.
Updates reference voltage supply for pins G5, H7, and H8 in Table 1.
Updates start-up timing recommendations with regard to TRST and M3_RESET in Section 2.7.1.
Adds input clock duty cycles in Table 20.
Updates PCI AC timings in Table 41.
Removes UTOPIA internal clock specifications in Table 52.
Updates JTAG timings in Table 56.
Clarifies connectivity guidelines for Ethernet pins in Section 3.3.4.
Miscellaneous pin connectivity guidelines were updated in Table 71.
Updates name of core subsystem reference manual.
2
June 2007
Corrected AA4 definition in Table 1. Changed TDM5TD3 to correct name TDM5TDAT.
Removed Figure 35 because the device does not support UTOPIA using an internal clock. Renumbered
subsequent figures.
Removed Section 3.5 Thermal Considerations. To be replaced with an application note.
3
Sep 2007
Updated M3 voltage range in Table 3.
Changed note in Table 7 for PLL power supplies.
DDR voltage designator changed from VDD to VDDDDR in Table 8, Table 10, Section 2.7.4.1, Section 2.7.4.2,
and Figure 11. Changed range on IOZ in Table 8 and Table 10.
Deleted text before Table 13 and added note 2 to input pin capacitance.
Deleted text before Table 14, added a 1 to the note, and added note 1 to input pin capacitance.
Deleted Section 2.6.5 on page 32 and renumbered subsequent subsections.
Deleted text before new Section 2.6.5.1.
Added a 1 to the note in Table 15 and added note 1 to input pin capacitance.
Deleted ac voltage rows from Table 16. Added note 1 to input pin capacitance.
Changed output high and low voltage levels in Table 17 and Table 18.
Deleted text before Table 19.
Added clock skew ranges in percent in Table 21.
Changed VREF to MVREF in Table 26.
Changed VDD to VDDIO in Table 41 Updated note 2.
Added note 4 to Table 42. Changed tTDMSHOX value.
Changed VDD to VDDGE in Figure 27 and Figure 30.
Changed the value of the data to clock out skew in Table 51.
Changed EE pin timing in Table 55.
Changed the head for the JTAG timing section, now Section 2.7.15.
Updated JTAG timing for TCK cycle time, TCK high phase, and boundary scan input data hold time in Table 56.
Added new Section 3.3 with guidelines for board layout for clock and timing signals. Renumbered subsequent
sections.
4
Sep 2007
Changed leakage current values in Table 13, Table 14, Table 11, Table 16, Table 17, Table 18, and Table 19
from –10 and 10
μa to –30 and 30 μa.
Change the minimum value of tMDDVKH in Table 45 from 5 ns to 7 ns.
Updated note 1 in Table 45.
5
Oct 2007
Corrected column numbering in Figure 3 and Figure 4.
Updated SPI signal names in Table 1.
6
Oct 2007
Updated SPI signal names in Table 1.
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