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參數(shù)資料
| 型號(hào)： | MSC8144VT800A |
| 廠商： | Freescale Semiconductor |
| 文件頁數(shù)： | 64/80頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC DSP QUAD 800MHZ 783FCBGA |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 系列： | StarCore |
| 類型： | SC3400 內(nèi)核 |
| 接口： | 以太網(wǎng)，I²C，SPI，TDM，UART，UTOPIA |
| 時(shí)鐘速率： | 800MHz |
| 非易失內(nèi)存： | 外部 |
| 芯片上RAM： | 10.5MB |
| 電壓 - 輸入/輸出： | 3.30V |
| 電壓 - 核心： | 1.00V |
| 工作溫度： | 0°C ~ 90°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 783-BBGA，F(xiàn)CBGA |
| 供應(yīng)商設(shè)備封裝： | 783-FCPBGA（29x29） |
| 包裝： | 托盤 |
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Hardware Design Considerations
MSC8144 Quad Core Digital Signal Processor Data Sheet, Rev. 16
Freescale Semiconductor
67
3.3
Clock and Timing Signal Board Layout Considerations
When laying out the system board, use the following guidelines:
Keep clock and timing signal paths as short as possible and route with 50
Ω impedance.
Use a serial termination resistor placed close to the clock buffer to minimize signal reflection. Use the following
equation to compute the resistor value:
Rterm = Rim – Rbuf
where Rim = trace characteristic impedance
Rbuf = clock buffer internal impedance.
Note:
See MSC8144 CLKIN and PCI_CLK_IN Board Layout (AN3440) for an example layout.
3.4
Note:
Although the package actually uses a ball grid array, the more conventional term pin is used to denote signal
connections in this discussion.
First, select the pin multiplexing mode to allocate the required I/O signals. Then use the guidelines presented in the following
subsections for board design and connections. The following conventions are used in describing the connectivity requirements:
1.
GND indicates using a 10 k
Ω pull-down resistor (recommended) or a direct connection to the ground plane. Direct
connections to the ground plane may yield DC current up to 50mA through the I/O supply that adds to overall power
consumption.
2.
VDD indicates using a 10 kΩ pull-up resistor (recommended) or a direct connection to the appropriate power supply.
Direct connections to the supply may yield DC current up to 50mA through the I/O supply that adds to overall power
consumption.
3.
Mandatory use of a pull-up or pull-down resistor it is clearly indicated as “pull-up/pull-down”.
4.
NC indicates “not connected” and means do not connect anything to the pin.
5.
The phrase “in use” indicates a typical pin connection for the required function.
Note:
Please see recommendations #1 and #2 as mandatory pull-down or pull-up connection for unused pins in case of
subset interface connection.
3.4.1
DDR Memory Related Pins
This section discusses the various scenarios that can be used with DDR1 and DDR2 memory.
Note:
For information about unused differential/non-differential pins in DDR1/DDR2 modes (that is, unused negative lines
of strobes in DDR1), please refer to Table 51.
3.4.1.1
DDR Interface Is Not Used
Table 51. Connectivity of DDR Related Pins When the DDR Interface Is Not Used
Signal Name
Pin Connection
MDQ[0–31]
NC
MDQS[0–3]
NC
MDQS[0–3]
NC
MA[0–15]
NC
MCK[0–2]
NC
MCK[0–2]
NC
MCS[0–1]
NC
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相關(guān)代理商/技術(shù)參數(shù) |
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|---|---|
| MSC8144VT800B | 制造商:Freescale Semiconductor 功能描述:DSP 32-Bit 800MHz 800MIPS 783-Pin FCBGA 制造商:Freescale Semiconductor 功能描述:PACSUN REV2.1 NON-E - Bulk 制造商:Freescale Semiconductor 功能描述:ENCRYPTION PACSUN R2.1 783FCPBGA |
| MSC81450M | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:RF & MICROWAVE TRANSISTORS AVIONICS APPLICATIONS |
| MSC8151 | 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:Single-Core Digital Signal Processor |
| MSC8151SAG1000B | 制造商:Freescale Semiconductor 功能描述:STARCORE DSP, 1X 1GHZ SC3850 CORES, MAPLE-B ACCELERATOR, DDR - Bulk 制造商:Freescale Semiconductor 功能描述:STARCORE DSP, 1X 1GHZ SC3850 CORES, MAPLE-B ACCELERATOR, DDR - Trays 制造商:Freescale Semiconductor 功能描述:IC DSP 1X 1GHZ SC3850 783FCBGA |
| MSC8151SVT1000B | 功能描述:數(shù)字信號(hào)處理器和控制器 - DSP, DSC Darwin RoHS:否 制造商:Microchip Technology 核心:dsPIC 數(shù)據(jù)總線寬度:16 bit 程序存儲(chǔ)器大小:16 KB 數(shù)據(jù) RAM 大小:2 KB 最大時(shí)鐘頻率:40 MHz 可編程輸入/輸出端數(shù)量:35 定時(shí)器數(shù)量:3 設(shè)備每秒兆指令數(shù):50 MIPs 工作電源電壓:3.3 V 最大工作溫度:+ 85 C 封裝 / 箱體:TQFP-44 安裝風(fēng)格:SMD/SMT |
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