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| 型號： | MSC8144VT800A |
| 廠商： | Freescale Semiconductor |
| 文件頁數(shù)： | 46/80頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC DSP QUAD 800MHZ 783FCBGA |
| 標準包裝： | 1 |
| 系列： | StarCore |
| 類型： | SC3400 內(nèi)核 |
| 接口： | 以太網(wǎng)，I²C，SPI，TDM，UART，UTOPIA |
| 時鐘速率： | 800MHz |
| 非易失內(nèi)存： | 外部 |
| 芯片上RAM： | 10.5MB |
| 電壓 - 輸入/輸出： | 3.30V |
| 電壓 - 核心： | 1.00V |
| 工作溫度： | 0°C ~ 90°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 783-BBGA，F(xiàn)CBGA |
| 供應(yīng)商設(shè)備封裝： | 783-FCPBGA（29x29） |
| 包裝： | 托盤 |
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MSC8144 Quad Core Digital Signal Processor Data Sheet, Rev. 16
Electrical Characteristics
Freescale Semiconductor
50
2.6.5.8
Eye Template Measurements
For the purpose of eye template measurements, the effects of a single-pole high pass filter with a 3 dB point at (baud
frequency)/1667 is applied to the jitter. The data pattern for template measurements is the continuous jitter test pattern (CJPAT)
defined in Annex 48A of IEEE Std. 802.3ae. All lanes of the LP-Serial link shall be active in both the transmit and receive
directions, and opposite ends of the links shall use asynchronous clocks. Four lane implementations shall use CJPAT as defined
in Annex 48A. Single lane implementations shall use the CJPAT sequence specified in Annex 48A for transmission on lane 0.
The amount of data represented in the eye shall be adequate to ensure that the bit error ratio is less than 10–12. The eye pattern
shall be measured with AC coupling and the compliance template centered at 0 Volts differential. The left and right edges of
the template shall be aligned with the mean zero crossing points of the measured data eye. The load for this test shall be 100
Ω
resistive
±5% differential to 2.5 GHz.
2.6.5.9
Jitter Test Measurements
For the purpose of jitter measurement, the effects of a single-pole high pass filter with a 3 dB point at (baud frequency)/1667 is
applied to the jitter. The data pattern for jitter measurements is the Continuous Jitter Test Pattern (CJPAT) pattern defined in
Annex 48A of IEEE Std. 802.3ae. All lanes of the LP-Serial link shall be active in both the transmit and receive directions, and
opposite ends of the links shall use asynchronous clocks. Four lane implementations shall use CJPAT as defined in Annex 48A.
Single lane implementations shall use the CJPAT sequence specified in Annex 48A for transmission on lane 0. Jitter shall be
measured with AC coupling and at 0 V differential. Jitter measurement for the transmitter (or for calibration of a jitter tolerance
setup) shall be performed with a test procedure resulting in a BER curve such as that described in Annex 48B of IEEE Std.
802.3ae.
2.6.5.10
Transmit Jitter
Transmit jitter is measured at the driver output when terminated into a load of 100
Ω resistive ±5% differential to 2.5 GHz.
2.6.5.11
Jitter Tolerance
Jitter tolerance is measured at the receiver using a jitter tolerance test signal. This signal is obtained by first producing the sum
of deterministic and random jitter defined in Section 2.6.5.9 and then adjusting the signal amplitude until the data eye contacts
the 6 points of the minimum eye opening of the receive template shown in Figure 14 and Table 35. Note that for this to occur,
the test signal must have vertical waveform symmetry about the average value and have horizontal symmetry (including jitter)
about the mean zero crossing. Eye template measurement requirements are as defined above. Random jitter is calibrated using
a high pass filter with a low frequency corner at 20 MHz and a 20 dB/decade roll-off below this. The required sinusoidal jitter
specified in Section 8.6 is then added to the signal and the test load is replaced by the receiver being tested.
2.6.6
PCI Timing
This section describes the general AC timing parameters of the PCI bus. Table 36 provides the PCI AC timing specifications.
Table 36. PCI AC Timing Specifications
Parameter
Symbol
33 MHz
66 MHz
Unit
Min
Max
Min
Max
Output delay
tPCVAL
2.0
11.0
1.0
6.0
ns
High-Z to Valid Output delay
tPCON
2.0
—
1.0
—
ns
Valid to High-Z Output delay
tPCOFF
—
28
—
14
ns
Input setup
tPCSU
7.0
—
3.0
—
ns
Input hold
tPCH
0—0
—
ns
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相關(guān)代理商/技術(shù)參數(shù) |
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|---|---|
| MSC8144VT800B | 制造商:Freescale Semiconductor 功能描述:DSP 32-Bit 800MHz 800MIPS 783-Pin FCBGA 制造商:Freescale Semiconductor 功能描述:PACSUN REV2.1 NON-E - Bulk 制造商:Freescale Semiconductor 功能描述:ENCRYPTION PACSUN R2.1 783FCPBGA |
| MSC81450M | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:RF & MICROWAVE TRANSISTORS AVIONICS APPLICATIONS |
| MSC8151 | 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:Single-Core Digital Signal Processor |
| MSC8151SAG1000B | 制造商:Freescale Semiconductor 功能描述:STARCORE DSP, 1X 1GHZ SC3850 CORES, MAPLE-B ACCELERATOR, DDR - Bulk 制造商:Freescale Semiconductor 功能描述:STARCORE DSP, 1X 1GHZ SC3850 CORES, MAPLE-B ACCELERATOR, DDR - Trays 制造商:Freescale Semiconductor 功能描述:IC DSP 1X 1GHZ SC3850 783FCBGA |
| MSC8151SVT1000B | 功能描述:數(shù)字信號處理器和控制器 - DSP, DSC Darwin RoHS:否 制造商:Microchip Technology 核心:dsPIC 數(shù)據(jù)總線寬度:16 bit 程序存儲器大小:16 KB 數(shù)據(jù) RAM 大小:2 KB 最大時鐘頻率:40 MHz 可編程輸入/輸出端數(shù)量:35 定時器數(shù)量:3 設(shè)備每秒兆指令數(shù):50 MIPs 工作電源電壓:3.3 V 最大工作溫度:+ 85 C 封裝 / 箱體:TQFP-44 安裝風(fēng)格:SMD/SMT |
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